[AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description

Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
llvm · Dec 13, 2022 · c27eded · c27eded
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diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst
diff --git a/llvm/docs/AMDGPU/gfx1030_fx_operand.rst b/llvm/docs/AMDGPU/gfx1030_fx_operand.rst
@@ -10,7 +10,7 @@
 FX Operand
 ==========
 
-This is an *f32* or *f16* operand depending on instruction modifiers:
+This is a *f32* or *f16* operand depending on instruction modifiers:
 
 * Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
-* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+* Location of the 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_hwreg.rst b/llvm/docs/AMDGPU/gfx1030_hwreg.rst
@@ -24,27 +24,27 @@ The bits of this operand have the following meaning:
 
 This operand may be specified as one of the following:
 
-* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
-* An *hwreg* value described below.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
+* An *hwreg* value which is described below.
 
-    ==================================== ============================================================================
+    ==================================== ===============================================================================
     Hwreg Value Syntax                   Description
-    ==================================== ============================================================================
-    hwreg({0..63})                       All bits of a register indicated by its *id*.
-    hwreg(<*name*>)                      All bits of a register indicated by its *name*.
-    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
-    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
-    ==================================== ============================================================================
+    ==================================== ===============================================================================
+    hwreg({0..63})                       All bits of a register indicated by the register *id*.
+    hwreg(<*name*>)                      All bits of a register indicated by the register *name*.
+    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by the register *id*, first bit *offset* and *size*.
+    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by the register *name*, first bit *offset* and *size*.
+    ==================================== ===============================================================================
 
 Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
 or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
 
-Defined register *names* include:
+Predefined register *names* include:
 
     ============================== ==========================================
     Name                           Description
     ============================== ==========================================
-    HW_REG_MODE                    Shader writeable mode bits.
+    HW_REG_MODE                    Shader writable mode bits.
     HW_REG_STATUS                  Shader read-only status.
     HW_REG_TRAPSTS                 Trap status.
     HW_REG_HW_ID1                  Id of wave, simd, compute unit, etc.

diff --git a/llvm/docs/AMDGPU/gfx1030_imm16_a04fb3.rst → llvm/docs/AMDGPU/gfx1030_imm16_0533c2.rst b/llvm/docs/AMDGPU/gfx1030_imm16_a04fb3.rst → llvm/docs/AMDGPU/gfx1030_imm16_0533c2.rst
@@ -5,9 +5,9 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_imm16_a04fb3:
+.. _amdgpu_synid_gfx1030_imm16_0533c2:
 
 imm16
 =====
 
-An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
diff --git a/llvm/docs/AMDGPU/gfx1030_imm16_73139a.rst → llvm/docs/AMDGPU/gfx1030_imm16_169952.rst b/llvm/docs/AMDGPU/gfx1030_imm16_73139a.rst → llvm/docs/AMDGPU/gfx1030_imm16_169952.rst
@@ -5,9 +5,9 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_imm16_73139a:
+.. _amdgpu_synid_gfx1030_imm16_169952:
 
 imm16
 =====
 
-An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 65535.
diff --git a/llvm/docs/AMDGPU/gfx1030_label.rst b/llvm/docs/AMDGPU/gfx1030_label.rst
@@ -10,11 +10,11 @@
 label
 =====
 
-A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+A branch target, which is a 16-bit signed integer treated as a PC-relative dword offset.
 
 This operand may be specified as one of the following:
 
-* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
 * A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
 
 Examples:

diff --git a/llvm/docs/AMDGPU/gfx1030_m_254bcb.rst → llvm/docs/AMDGPU/gfx1030_m_28b494.rst b/llvm/docs/AMDGPU/gfx1030_m_254bcb.rst → llvm/docs/AMDGPU/gfx1030_m_28b494.rst
@@ -5,9 +5,9 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_m_254bcb:
+.. _amdgpu_synid_gfx1030_m_28b494:
 
 m
 =
 
-This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
+This operand may be used with an integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_m_f5d306.rst → llvm/docs/AMDGPU/gfx1030_m_c141fc.rst b/llvm/docs/AMDGPU/gfx1030_m_f5d306.rst → llvm/docs/AMDGPU/gfx1030_m_c141fc.rst
@@ -5,9 +5,9 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_m_f5d306:
+.. _amdgpu_synid_gfx1030_m_c141fc:
 
 m
 =
 
-This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+This operand may be used with floating-point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_msg.rst b/llvm/docs/AMDGPU/gfx1030_msg.rst
@@ -24,8 +24,8 @@ A 16-bit message code. The bits of this operand have the following meaning:
 
 This operand may be specified as one of the following:
 
-* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
-* A *sendmsg* value described below.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
+* A *sendmsg* value which is described below.
 
     ==================================== ====================================================
     Sendmsg Value Syntax                 Description
@@ -40,7 +40,7 @@ This operand may be specified as one of the following:
 
 *Op* may be specified using operation *name* or operation *id*.
 
-Stream *id* is an integer in the range 0..3.
+Stream *id* is an integer in the range from 0 to 3.
 
 Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
 or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
@@ -73,7 +73,7 @@ Each message type supports specific operations:
 *Sendmsg* arguments are validated depending on how *type* value is specified:
 
 * If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
-* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
+* If message *type* is specified as a number, each argument must not exceed the corresponding value range (see the first table).
 
 Examples:
 

diff --git a/llvm/docs/AMDGPU/gfx1030_sbase_010ce0.rst → llvm/docs/AMDGPU/gfx1030_sbase_b0aa25.rst b/llvm/docs/AMDGPU/gfx1030_sbase_010ce0.rst → llvm/docs/AMDGPU/gfx1030_sbase_b0aa25.rst
@@ -5,12 +5,12 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_sbase_010ce0:
+.. _amdgpu_synid_gfx1030_sbase_b0aa25:
 
 sbase
 =====
 
-A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size, and a stride.
 
 *Size:* 4 dwords.
 

diff --git a/llvm/docs/AMDGPU/gfx1030_soffset_d01a5c.rst → llvm/docs/AMDGPU/gfx1030_soffset_0f304c.rst b/llvm/docs/AMDGPU/gfx1030_soffset_d01a5c.rst → llvm/docs/AMDGPU/gfx1030_soffset_0f304c.rst
@@ -5,12 +5,12 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_soffset_d01a5c:
+.. _amdgpu_synid_gfx1030_soffset_0f304c:
 
 soffset
 =======
 
-An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate.
+An unsigned offset from the base address. May be specified as either a register or a 20-bit immediate.
 
 Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both.
 

diff --git a/llvm/docs/AMDGPU/gfx1030_srsrc_e73d16.rst → llvm/docs/AMDGPU/gfx1030_srsrc_80eef6.rst b/llvm/docs/AMDGPU/gfx1030_srsrc_e73d16.rst → llvm/docs/AMDGPU/gfx1030_srsrc_80eef6.rst
@@ -5,12 +5,12 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_srsrc_e73d16:
+.. _amdgpu_synid_gfx1030_srsrc_80eef6:
 
 srsrc
 =====
 
-Buffer resource constant which defines the address and characteristics of the buffer in memory.
+Buffer resource constant, which defines the address and characteristics of the buffer in memory.
 
 *Size:* 4 dwords.
 

diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_7a07c6.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_7a07c6.rst
diff --git a/llvm/docs/AMDGPU/gfx1030_tgt.rst b/llvm/docs/AMDGPU/gfx1030_tgt.rst
@@ -22,3 +22,10 @@ An export target:
     prim               Copy primitive (connectivity) data.
     null               Copy nothing.
     ================== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+  exp pos3 v1, v2, v3, v4
+  exp mrt0 v1, v2, v3, v4
diff --git a/llvm/docs/AMDGPU/gfx1030_type_deviation.rst b/llvm/docs/AMDGPU/gfx1030_type_deviation.rst
@@ -10,4 +10,4 @@
 Type Deviation
 ==============
 
-*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies actual operand *type*.
+The *type* of this operand differs from the *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies the actual operand *type*.
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_49d53a.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_49d53a.rst
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_a5639c.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_a5639c.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_a5639c:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 1-12 dwords. Actual size depends on opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_cdc744.rst → llvm/docs/AMDGPU/gfx1030_vaddr_c5ab43.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_cdc744.rst → llvm/docs/AMDGPU/gfx1030_vaddr_c5ab43.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_vaddr_cdc744:
+.. _amdgpu_synid_gfx1030_vaddr_c5ab43:
 
 vaddr
 =====
@@ -14,9 +14,17 @@ Image address which includes from one to four dimensional coordinates and other
 
 This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
 
-*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+*Size:* 8-12 dwords. Actual size depends on opcode and :ref:`a16<amdgpu_synid_a16>`.
 
-* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
-* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
+
+
+  Examples:
+
+  .. parsed-literal::
+
+    image_bvh_intersect_ray   v[4:7], v[9:16], s[4:7]
+    image_bvh64_intersect_ray v[5:8], v[1:12], s[8:11]
+    image_bvh_intersect_ray   v[39:42], [v5, v4, v2, v1, v7, v3, v0, v6], s[12:15] a16
+    image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40, v42], s[12:15]
 
 *Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_15d255.rst → llvm/docs/AMDGPU/gfx1030_vdata_21b58d.rst b/llvm/docs/AMDGPU/gfx1030_vdata_15d255.rst → llvm/docs/AMDGPU/gfx1030_vdata_21b58d.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_vdata_15d255:
+.. _amdgpu_synid_gfx1030_vdata_21b58d:
 
 vdata
 =====
@@ -14,7 +14,7 @@ Image data to store by an *image_store* instruction.
 
 *Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
 
-* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16<amdgpu_synid_d16>`.
 * :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
 
 *Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_890652.rst → llvm/docs/AMDGPU/gfx1030_vdata_2d6239.rst b/llvm/docs/AMDGPU/gfx1030_vdata_890652.rst → llvm/docs/AMDGPU/gfx1030_vdata_2d6239.rst
@@ -5,14 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_vdata_890652:
+.. _amdgpu_synid_gfx1030_vdata_2d6239:
 
 vdata
 =====
 
 Input data for an atomic instruction.
 
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
 
 * If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
 

diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_16d321.rst → llvm/docs/AMDGPU/gfx1030_vdata_4b260e.rst b/llvm/docs/AMDGPU/gfx1030_vdata_16d321.rst → llvm/docs/AMDGPU/gfx1030_vdata_4b260e.rst
@@ -5,14 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_vdata_16d321:
+.. _amdgpu_synid_gfx1030_vdata_4b260e:
 
 vdata
 =====
 
 Input data for an atomic instruction.
 
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
 
 * If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
 

diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_a9ff5a.rst → llvm/docs/AMDGPU/gfx1030_vdata_84fab6.rst b/llvm/docs/AMDGPU/gfx1030_vdata_a9ff5a.rst → llvm/docs/AMDGPU/gfx1030_vdata_84fab6.rst
@@ -5,14 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx1030_vdata_a9ff5a:
+.. _amdgpu_synid_gfx1030_vdata_84fab6:
 
 vdata
 =====
 
 Input data for an atomic instruction.
 
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
 
 * If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
 
@@ -21,6 +21,6 @@ Optionally may serve as an output data:
 * :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
 
 
-  Note: the surface data format is indicated in the image resource constant but not in the instruction.
+  Note: the surface data format is indicated in the image resource constant, but not in the instruction.
 
 *Operands:* :ref:`v<amdgpu_synid_v>`