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[AMDGPU] Remove cndmask from readsExecAsData
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Differential Revision: https://reviews.llvm.org/D117909
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@rampitec
rampitec committed Jan 24, 2022
1 parent b1af01f commit c27f8fb
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5 changes: 0 additions & 5 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -138,11 +138,6 @@ static bool readsExecAsData(const MachineInstr &MI) {
default:
break;
case AMDGPU::V_READFIRSTLANE_B32:
case AMDGPU::V_CNDMASK_B64_PSEUDO:
case AMDGPU::V_CNDMASK_B32_dpp:
case AMDGPU::V_CNDMASK_B32_e32:
case AMDGPU::V_CNDMASK_B32_e64:
case AMDGPU::V_CNDMASK_B32_sdwa:
return true;
}

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144 changes: 0 additions & 144 deletions llvm/test/CodeGen/AMDGPU/licm-valu.mir
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Expand Up @@ -99,147 +99,3 @@ body: |
bb.2:
S_ENDPGM 0
...
---
name: no_hoist_cndmask_e64
tracksRegLiveness: true
body: |
; GCN-LABEL: name: no_hoist_cndmask_e64
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[DEF]], 0, [[DEF]], [[DEF1]], implicit $exec
; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: S_ENDPGM 0
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF
S_BRANCH %bb.1
bb.1:
%2:vgpr_32 = V_CNDMASK_B32_e64 0, %0, 0, %0, %1, implicit $exec
$exec = S_OR_B64 $exec, 1, implicit-def $scc
S_CBRANCH_EXECNZ %bb.1, implicit $exec
S_BRANCH %bb.2
bb.2:
S_ENDPGM 0
...
---
name: no_hoist_cndmask_e32
tracksRegLiveness: true
body: |
; GCN-LABEL: name: no_hoist_cndmask_e32
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[V_CNDMASK_B32_e32_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e32 [[DEF]], [[DEF]], implicit undef $vcc, implicit $exec
; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: S_ENDPGM 0
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF
S_BRANCH %bb.1
bb.1:
%2:vgpr_32 = V_CNDMASK_B32_e32 %0, %0, implicit undef $vcc, implicit $exec
$exec = S_OR_B64 $exec, 1, implicit-def $scc
S_CBRANCH_EXECNZ %bb.1, implicit $exec
S_BRANCH %bb.2
bb.2:
S_ENDPGM 0
...
---
name: no_hoist_cndmask_dpp
tracksRegLiveness: true
body: |
; GCN-LABEL: name: no_hoist_cndmask_dpp
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[V_CNDMASK_B32_dpp:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_dpp [[DEF]], 0, [[DEF]], 0, [[DEF]], 1, 15, 15, 10, implicit $exec, implicit undef $vcc
; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: S_ENDPGM 0
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF
S_BRANCH %bb.1
bb.1:
%2:vgpr_32 = V_CNDMASK_B32_dpp %0:vgpr_32, 0, %0:vgpr_32, 0, %0:vgpr_32, 1, 15, 15, 10, implicit $exec, implicit undef $vcc
$exec = S_OR_B64 $exec, 1, implicit-def $scc
S_CBRANCH_EXECNZ %bb.1, implicit $exec
S_BRANCH %bb.2
bb.2:
S_ENDPGM 0
...
---
name: no_hoist_cndmask_sdwa
tracksRegLiveness: true
body: |
; GCN-LABEL: name: no_hoist_cndmask_sdwa
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[V_CNDMASK_B32_sdwa:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_sdwa 0, [[DEF]], 0, [[DEF]], 0, 0, 0, 0, 0, implicit $exec, implicit undef $vcc
; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: S_ENDPGM 0
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_64_xexec = IMPLICIT_DEF
S_BRANCH %bb.1
bb.1:
%2:vgpr_32 = V_CNDMASK_B32_sdwa 0, %0:vgpr_32, 0, %0:vgpr_32, 0, 0, 0, 0, 0, implicit $exec, implicit undef $vcc
$exec = S_OR_B64 $exec, 1, implicit-def $scc
S_CBRANCH_EXECNZ %bb.1, implicit $exec
S_BRANCH %bb.2
bb.2:
S_ENDPGM 0
...

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