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Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
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This patch appears to trigger very large compile time increases in
halide builds.

llvm-svn: 357116
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@niravhdave
niravhdave committed Mar 27, 2019
1 parent 07b74c3 commit c6dfaa0
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Showing 49 changed files with 3,701 additions and 3,280 deletions.
3 changes: 0 additions & 3 deletions llvm/include/llvm/CodeGen/SelectionDAG.h
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Original file line number Diff line number Diff line change
Expand Up @@ -297,9 +297,6 @@ class SelectionDAG {

/// The node N that was updated.
virtual void NodeUpdated(SDNode *N);

/// The node N that was inserted.
virtual void NodeInserted(SDNode *N);
};

struct DAGNodeDeletedListener : public DAGUpdateListener {
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12 changes: 0 additions & 12 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -643,16 +643,6 @@ class WorklistRemover : public SelectionDAG::DAGUpdateListener {
}
};

class WorklistInserter : public SelectionDAG::DAGUpdateListener {
DAGCombiner &DC;

public:
explicit WorklistInserter(DAGCombiner &dc)
: SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}

void NodeInserted(SDNode *N) override { DC.AddToWorklist(N); }
};

} // end anonymous namespace

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1405,8 +1395,6 @@ void DAGCombiner::Run(CombineLevel AtLevel) {
LegalOperations = Level >= AfterLegalizeVectorOps;
LegalTypes = Level >= AfterLegalizeTypes;

WorklistInserter AddNodes(*this);

// Add all the dag nodes to the worklist.
for (SDNode &Node : DAG.allnodes())
AddToWorklist(&Node);
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3 changes: 0 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,6 @@ static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) {
// Default null implementations of the callbacks.
void SelectionDAG::DAGUpdateListener::NodeDeleted(SDNode*, SDNode*) {}
void SelectionDAG::DAGUpdateListener::NodeUpdated(SDNode*) {}
void SelectionDAG::DAGUpdateListener::NodeInserted(SDNode *) {}

void SelectionDAG::DAGNodeDeletedListener::anchor() {}

Expand Down Expand Up @@ -834,8 +833,6 @@ void SelectionDAG::InsertNode(SDNode *N) {
N->PersistentId = NextPersistentId++;
VerifySDNode(N);
#endif
for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
DUL->NodeInserted(N);
}

/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
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Expand Up @@ -156,7 +156,8 @@ define <4 x i32> @out_constant_mone_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4
define <4 x i32> @in_constant_mone_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
; CHECK-LABEL: in_constant_mone_vary_invmask:
; CHECK: // %bb.0:
; CHECK-NEXT: orn v0.16b, v1.16b, v2.16b
; CHECK-NEXT: and v0.16b, v1.16b, v2.16b
; CHECK-NEXT: orn v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -313,7 +313,7 @@ entry:
; CHECK-COMMON-LABEL: mul_with_neg_imm
; CHECK-COMMON-NOT: uxtb
; CHECK-COMMON: and [[BIT0:r[0-9]+]], r0, #1
; CHECK-COMMON: orr.w [[MUL32:r[0-9]+]], [[BIT0]], [[BIT0]], lsl #5
; CHECK-COMMON: add.w [[MUL32:r[0-9]+]], [[BIT0]], [[BIT0]], lsl #5
; CHECK-COMMON: cmp.w r0, [[MUL32]], lsl #2
define void @mul_with_neg_imm(i32, i32* %b) {
entry:
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,8 @@ target triple = "thumbv7em-arm-none-eabi"
define arm_aapcs_vfpcc void @test(i8* %v50) #0 {
; CHECK-LABEL: test:
; CHECK: @ %bb.0:
; CHECK-NEXT: movw r1, #65534
; CHECK-NEXT: strh.w r1, [r0, #510]
; CHECK-NEXT: movw r1, #64506
; CHECK-NEXT: movt r1, #65020
; CHECK-NEXT: str.w r1, [r0, #506]
Expand Down Expand Up @@ -92,8 +94,6 @@ define arm_aapcs_vfpcc void @test(i8* %v50) #0 {
; CHECK-NEXT: movw r1, #36750
; CHECK-NEXT: movt r1, #37264
; CHECK-NEXT: str.w r1, [r0, #398]
; CHECK-NEXT: movw r1, #65534
; CHECK-NEXT: strh.w r1, [r0, #510]
; CHECK-NEXT: movw r1, #35722
; CHECK-NEXT: movt r1, #36236
; CHECK-NEXT: str.w r1, [r0, #394]
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/ARM/vdup.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -430,6 +430,7 @@ define <2 x float> @check_f32(<4 x float> %v) nounwind {
; CHECK-LABEL: check_f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d17, r2, r3
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: vdup.32 d16, d17[1]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
Expand All @@ -443,6 +444,7 @@ define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
; CHECK-LABEL: check_i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d17, r2, r3
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: vdup.32 d16, d17[1]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
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24 changes: 12 additions & 12 deletions llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -155,12 +155,12 @@ define i8* @_Z3fooi(i32 signext %Letter) {
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: daddiu $sp, $sp, -16
; MIPS64R2-NEXT: .cfi_def_cfa_offset 16
; MIPS64R2-NEXT: sltiu $1, $4, 7
; MIPS64R2-NEXT: dext $2, $4, 0, 32
; MIPS64R2-NEXT: sltiu $1, $2, 7
; MIPS64R2-NEXT: beqz $1, .LBB0_3
; MIPS64R2-NEXT: sw $4, 4($sp)
; MIPS64R2-NEXT: .LBB0_1: # %entry
; MIPS64R2-NEXT: dext $1, $4, 0, 32
; MIPS64R2-NEXT: dsll $1, $1, 3
; MIPS64R2-NEXT: dsll $1, $2, 3
; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0)
; MIPS64R2-NEXT: daddiu $2, $2, %higher(.LJTI0_0)
; MIPS64R2-NEXT: dsll $2, $2, 16
Expand Down Expand Up @@ -250,12 +250,12 @@ define i8* @_Z3fooi(i32 signext %Letter) {
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: daddiu $sp, $sp, -16
; MIPS64R6-NEXT: .cfi_def_cfa_offset 16
; MIPS64R6-NEXT: sltiu $1, $4, 7
; MIPS64R6-NEXT: dext $2, $4, 0, 32
; MIPS64R6-NEXT: sltiu $1, $2, 7
; MIPS64R6-NEXT: beqz $1, .LBB0_3
; MIPS64R6-NEXT: sw $4, 4($sp)
; MIPS64R6-NEXT: .LBB0_1: # %entry
; MIPS64R6-NEXT: dext $1, $4, 0, 32
; MIPS64R6-NEXT: dsll $1, $1, 3
; MIPS64R6-NEXT: dsll $1, $2, 3
; MIPS64R6-NEXT: lui $2, %highest(.LJTI0_0)
; MIPS64R6-NEXT: daddiu $2, $2, %higher(.LJTI0_0)
; MIPS64R6-NEXT: dsll $2, $2, 16
Expand Down Expand Up @@ -472,12 +472,12 @@ define i8* @_Z3fooi(i32 signext %Letter) {
; PIC-MIPS64R2-NEXT: lui $1, %hi(%neg(%gp_rel(_Z3fooi)))
; PIC-MIPS64R2-NEXT: daddu $1, $1, $25
; PIC-MIPS64R2-NEXT: daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))
; PIC-MIPS64R2-NEXT: sltiu $1, $4, 7
; PIC-MIPS64R2-NEXT: dext $3, $4, 0, 32
; PIC-MIPS64R2-NEXT: sltiu $1, $3, 7
; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_3
; PIC-MIPS64R2-NEXT: sw $4, 4($sp)
; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry
; PIC-MIPS64R2-NEXT: dext $1, $4, 0, 32
; PIC-MIPS64R2-NEXT: dsll $1, $1, 3
; PIC-MIPS64R2-NEXT: dsll $1, $3, 3
; PIC-MIPS64R2-NEXT: ld $3, %got_page(.LJTI0_0)($2)
; PIC-MIPS64R2-NEXT: daddu $1, $1, $3
; PIC-MIPS64R2-NEXT: ld $1, %got_ofst(.LJTI0_0)($1)
Expand Down Expand Up @@ -535,12 +535,12 @@ define i8* @_Z3fooi(i32 signext %Letter) {
; PIC-MIPS64R6-NEXT: lui $1, %hi(%neg(%gp_rel(_Z3fooi)))
; PIC-MIPS64R6-NEXT: daddu $1, $1, $25
; PIC-MIPS64R6-NEXT: daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))
; PIC-MIPS64R6-NEXT: sltiu $1, $4, 7
; PIC-MIPS64R6-NEXT: dext $3, $4, 0, 32
; PIC-MIPS64R6-NEXT: sltiu $1, $3, 7
; PIC-MIPS64R6-NEXT: beqz $1, .LBB0_3
; PIC-MIPS64R6-NEXT: sw $4, 4($sp)
; PIC-MIPS64R6-NEXT: .LBB0_1: # %entry
; PIC-MIPS64R6-NEXT: dext $1, $4, 0, 32
; PIC-MIPS64R6-NEXT: dsll $1, $1, 3
; PIC-MIPS64R6-NEXT: dsll $1, $3, 3
; PIC-MIPS64R6-NEXT: ld $3, %got_page(.LJTI0_0)($2)
; PIC-MIPS64R6-NEXT: daddu $1, $1, $3
; PIC-MIPS64R6-NEXT: ld $1, %got_ofst(.LJTI0_0)($1)
Expand Down
76 changes: 38 additions & 38 deletions llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -588,16 +588,16 @@ define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, <
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 32(r3)
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr
entry:
%0 = sitofp <8 x i16> %a to <8 x double>
Expand Down Expand Up @@ -738,50 +738,50 @@ define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result,
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v2, 0, r5
; CHECK-BE-NEXT: lxv v5, 0(r4)
; CHECK-BE-NEXT: lxv v6, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: lxv v1, 16(r4)
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: xxlxor v0, v0, v0
; CHECK-BE-NEXT: vperm v1, v0, v5, v2
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: vperm v0, v5, v4, v2
; CHECK-BE-NEXT: lxvx v3, 0, r5
; CHECK-BE-NEXT: vperm v2, v0, v6, v2
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_2@toc@l
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: lxvx v4, 0, r5
; CHECK-BE-NEXT: vextsh2d v1, v1
; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: vperm v2, v0, v6, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v1
; CHECK-BE-NEXT: vperm v1, v0, v5, v3
; CHECK-BE-NEXT: vperm v2, v5, v1, v2
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs4, v2
; CHECK-BE-NEXT: vperm v2, v0, v6, v4
; CHECK-BE-NEXT: vextsh2d v1, v1
; CHECK-BE-NEXT: xvcvsxddp vs1, v1
; CHECK-BE-NEXT: vperm v1, v0, v5, v4
; CHECK-BE-NEXT: stxv vs3, 80(r3)
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs2, v2
; CHECK-BE-NEXT: vperm v2, v5, v1, v3
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs5, v2
; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: lxvx v2, 0, r4
; CHECK-BE-NEXT: vperm v3, v5, v5, v2
; CHECK-BE-NEXT: vperm v2, v6, v6, v2
; CHECK-BE-NEXT: vextsh2d v1, v1
; CHECK-BE-NEXT: stxv vs4, 96(r3)
; CHECK-BE-NEXT: xvcvsxddp vs0, v0
; CHECK-BE-NEXT: vperm v0, v5, v4, v3
; CHECK-BE-NEXT: vperm v3, v4, v4, v2
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs1, v0
; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v1, v1, v2
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs6, v2
; CHECK-BE-NEXT: vperm v2, v1, v1, v3
; CHECK-BE-NEXT: vperm v4, v4, v4, v3
; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs2, v1
; CHECK-BE-NEXT: stxv vs2, 48(r3)
; CHECK-BE-NEXT: stxv vs5, 112(r3)
; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 64(r3)
; CHECK-BE-NEXT: stxv vs1, 32(r3)
; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs6, 0(r3)
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: blr
entry:
%a = load <16 x i16>, <16 x i16>* %0, align 32
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -555,16 +555,16 @@ define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result,
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 32(r3)
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr
entry:
%0 = sitofp <16 x i8> %a to <16 x float>
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -626,16 +626,16 @@ define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 32(r3)
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <8 x i8>
Expand Down Expand Up @@ -814,43 +814,43 @@ define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result,
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: stxv vs1, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs2, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: stxv vs2, 48(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs3, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs3, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: stxv vs3, 64(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs4, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: stxv vs4, 80(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs5, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: stxv vs5, 96(r3)
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs6, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: blr
entry:
%0 = sitofp <16 x i8> %a to <16 x double>
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