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[SVE2.1][Clang][LLVM]Add 128bits builtin in Clang and LLVM intrinisc (#…
…71930) This patch implements the builtins in Clang and the LLVM-IR intrinsic for the following: EXTQ // Variants are also available for: // _s8, _s16, _u16, _s32, _u32, _s64, _u64 // _bf16, _f16, _f32, _f64 svuint8_t svextq_lane[_u8](svuint8_t zdn, svuint8_t zm, uint64_t imm); TBLQ and TBXQ // Variants are also available for: // _u8, _u16, _s16, _u32, _s32, _u64, _s64 // _bf16, _f16, _f32, _f64 svint8_t svtblq[_s8](svint8_t zn, svuint8_t zm); svint8_t svtbxq[_s8](svint8_t zn, svuint8_t zm); UZPQ1, UZPQ2, ZIPQ1 and ZIPQ2 // Variants are also available for: // _s8, _u16, _s16, _u32, _s32, _u64, _s64 // _bf16, _f16, _f32, _f64 svuint8_t svuzpq1[_u8](svuint8_t zn, svuint8_t zm); svuint8_t svuzpq2[_u8](svuint8_t zn, svuint8_t zm); svuint8_t svzipq1[_u8](svuint8_t zn, svuint8_t zm); svuint8_t svzipq2[_u8](svuint8_t zn, svuint8_t zm); PMOV // Variants are available for: // _s8, _u16, _s16, _s32, _u32, _s64, _u64 svbool_t svpmov_lane[_u8](svuint8_t zn, uint64_t imm); svbool_t svpmov[_u8](svuint8_t zn); // The immediate is zero svuint8_t svpmov_u8_z(svbool_t pn); // The immediate is zero // Variants are available for: // _s16, _s32, _u32, _s64, _u64 svuint16_t svpmov_lane[_u16]_m(svuint16_t zd, svbool_t pn, uint64_t imm); According to the PR#257[1] [1]ARM-software/acle#257 Co-authored-by: Hassnaa Hamdi <hassnaa.hamdi@arm.com>
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clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_extq.c
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 | ||
// REQUIRES: aarch64-registered-target | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -target-feature +bf16\ | ||
// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -target-feature +bf16\ | ||
// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -target-feature +bf16\ | ||
// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK | ||
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -target-feature +bf16\ | ||
// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
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#include <arm_sve.h> | ||
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#ifdef SVE_OVERLOADED_FORMS | ||
// A simple used,unused... macro, long enough to represent any SVE builtin. | ||
#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 | ||
#else | ||
#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 | ||
#endif | ||
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// CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svextq_lane_u8 | ||
// CHECK-SAME: (<vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]]) #[[ATTR0:[0-9]+]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.extq.lane.nxv16i8(<vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 0) | ||
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 16 x i8> @_Z19test_svextq_lane_u8u11__SVUint8_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]]) #[[ATTR0:[0-9]+]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.extq.lane.nxv16i8(<vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 0) | ||
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
// | ||
svuint8_t test_svextq_lane_u8(svuint8_t zn, svuint8_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _u8,,)(zn, zm, 0); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svextq_lane_s8 | ||
// CHECK-SAME: (<vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.extq.lane.nxv16i8(<vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 4) | ||
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 16 x i8> @_Z19test_svextq_lane_s8u10__SVInt8_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.extq.lane.nxv16i8(<vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]], i32 4) | ||
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
// | ||
svint8_t test_svextq_lane_s8(svint8_t zn, svint8_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _s8,,)(zn, zm, 4); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 8 x i16> @test_svextq_lane_u16 | ||
// CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 8 x i16> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.extq.lane.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i16> [[ZM]], i32 1) | ||
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 8 x i16> @_Z20test_svextq_lane_u16u12__SVUint16_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 8 x i16> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.extq.lane.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i16> [[ZM]], i32 1) | ||
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] | ||
// | ||
svuint16_t test_svextq_lane_u16(svuint16_t zn, svuint16_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _u16,,)(zn, zm, 1); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 8 x i16> @test_svextq_lane_s16 | ||
// CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 8 x i16> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.extq.lane.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i16> [[ZM]], i32 5) | ||
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 8 x i16> @_Z20test_svextq_lane_s16u11__SVInt16_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 8 x i16> [[ZN:%.*]], <vscale x 8 x i16> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.extq.lane.nxv8i16(<vscale x 8 x i16> [[ZN]], <vscale x 8 x i16> [[ZM]], i32 5) | ||
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] | ||
// | ||
svint16_t test_svextq_lane_s16(svint16_t zn, svint16_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _s16,,)(zn, zm, 5); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 4 x i32> @test_svextq_lane_u32 | ||
// CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 4 x i32> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.extq.lane.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i32> [[ZM]], i32 2) | ||
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 4 x i32> @_Z20test_svextq_lane_u32u12__SVUint32_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 4 x i32> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.extq.lane.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i32> [[ZM]], i32 2) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
svuint32_t test_svextq_lane_u32(svuint32_t zn, svuint32_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _u32,,)(zn, zm, 2); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 4 x i32> @test_svextq_lane_s32 | ||
// CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 4 x i32> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.extq.lane.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i32> [[ZM]], i32 6) | ||
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 4 x i32> @_Z20test_svextq_lane_s32u11__SVInt32_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 4 x i32> [[ZN:%.*]], <vscale x 4 x i32> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.extq.lane.nxv4i32(<vscale x 4 x i32> [[ZN]], <vscale x 4 x i32> [[ZM]], i32 6) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] | ||
// | ||
svint32_t test_svextq_lane_s32(svint32_t zn, svint32_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _s32,,)(zn, zm, 6); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 2 x i64> @test_svextq_lane_u64 | ||
// CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 2 x i64> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.extq.lane.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i64> [[ZM]], i32 3) | ||
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 2 x i64> @_Z20test_svextq_lane_u64u12__SVUint64_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 2 x i64> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.extq.lane.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i64> [[ZM]], i32 3) | ||
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] | ||
// | ||
svuint64_t test_svextq_lane_u64(svuint64_t zn, svuint64_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _u64,,)(zn, zm, 3); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 2 x i64> @test_svextq_lane_s64 | ||
// CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 2 x i64> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.extq.lane.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i64> [[ZM]], i32 7) | ||
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 2 x i64> @_Z20test_svextq_lane_s64u11__SVInt64_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 2 x i64> [[ZN:%.*]], <vscale x 2 x i64> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.extq.lane.nxv2i64(<vscale x 2 x i64> [[ZN]], <vscale x 2 x i64> [[ZM]], i32 7) | ||
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] | ||
// | ||
svint64_t test_svextq_lane_s64(svint64_t zn, svint64_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _s64,,)(zn, zm, 7); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svextq_lane_f16 | ||
// CHECK-SAME: (<vscale x 8 x half> [[ZN:%.*]], <vscale x 8 x half> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.extq.lane.nxv8f16(<vscale x 8 x half> [[ZN]], <vscale x 8 x half> [[ZM]], i32 8) | ||
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 8 x half> @_Z20test_svextq_lane_f16u13__SVFloat16_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 8 x half> [[ZN:%.*]], <vscale x 8 x half> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.extq.lane.nxv8f16(<vscale x 8 x half> [[ZN]], <vscale x 8 x half> [[ZM]], i32 8) | ||
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
// | ||
svfloat16_t test_svextq_lane_f16(svfloat16_t zn, svfloat16_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _f16,,)(zn, zm, 8); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 4 x float> @test_svextq_lane_f32 | ||
// CHECK-SAME: (<vscale x 4 x float> [[ZN:%.*]], <vscale x 4 x float> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.extq.lane.nxv4f32(<vscale x 4 x float> [[ZN]], <vscale x 4 x float> [[ZM]], i32 9) | ||
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 4 x float> @_Z20test_svextq_lane_f32u13__SVFloat32_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 4 x float> [[ZN:%.*]], <vscale x 4 x float> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.extq.lane.nxv4f32(<vscale x 4 x float> [[ZN]], <vscale x 4 x float> [[ZM]], i32 9) | ||
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] | ||
// | ||
svfloat32_t test_svextq_lane_f32(svfloat32_t zn, svfloat32_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _f32,,)(zn, zm, 9); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 2 x double> @test_svextq_lane_f64 | ||
// CHECK-SAME: (<vscale x 2 x double> [[ZN:%.*]], <vscale x 2 x double> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.extq.lane.nxv2f64(<vscale x 2 x double> [[ZN]], <vscale x 2 x double> [[ZM]], i32 10) | ||
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 2 x double> @_Z20test_svextq_lane_f64u13__SVFloat64_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 2 x double> [[ZN:%.*]], <vscale x 2 x double> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.extq.lane.nxv2f64(<vscale x 2 x double> [[ZN]], <vscale x 2 x double> [[ZM]], i32 10) | ||
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] | ||
// | ||
svfloat64_t test_svextq_lane_f64(svfloat64_t zn, svfloat64_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _f64,,)(zn, zm, 10); | ||
} | ||
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// CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svextq_lane_bf16 | ||
// CHECK-SAME: (<vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.lane.nxv8bf16(<vscale x 8 x bfloat> [[ZN]], <vscale x 8 x bfloat> [[ZM]], i32 11) | ||
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
// | ||
// CPP-CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @_Z21test_svextq_lane_bf16u14__SVBfloat16_tS_ | ||
// CPP-CHECK-SAME: (<vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]]) #[[ATTR0]] { | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.lane.nxv8bf16(<vscale x 8 x bfloat> [[ZN]], <vscale x 8 x bfloat> [[ZM]], i32 11) | ||
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
// | ||
svbfloat16_t test_svextq_lane_bf16(svbfloat16_t zn, svbfloat16_t zm) { | ||
return SVE_ACLE_FUNC(svextq_lane, _bf16,,)(zn, zm, 11); | ||
} |
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