[RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadT…

…oRVV

We returned the input chain instead of the output chain from the
new load. This bypasses the load in the chain. I haven't found a
good way to test this yet. IR order prevents my initial attempts
at causing reordering.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -3217,7 +3217,7 @@ SDValue RISCVTargetLowering::lowerFixedLengthVectorMaskedLoadToRVV(
                               Load->getMemoryVT(), Load->getMemOperand());
 
   SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget);
-  return DAG.getMergeValues({Result, Load->getChain()}, DL);
+  return DAG.getMergeValues({Result, NewLoad.getValue(1)}, DL);
 }
 
 SDValue RISCVTargetLowering::lowerFixedLengthVectorMaskedStoreToRVV(