[RISCV] Replace XLenVT in RV64 only pattern with i64. NFC

llvm · Nov 21, 2023 · c9fd76f · c9fd76f
1 parent e1ee0e8
commit c9fd76f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2013,7 +2013,7 @@ def : Pat<(XLenVT (abs GPR:$rs1)),
 let Predicates = [HasShortForwardBranchOpt, IsRV64] in
 def : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32),
           (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2,
-           (XLenVT GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;
+           (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;
 
 //===----------------------------------------------------------------------===//
 // Experimental RV64 i32 legalization patterns.