[AArch64] Additional testing for i128 and non-temporal loads/stores u…

…ndef BE. NFC

llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll

@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+; RUN: llc -mtriple=aarch64_be %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 
 @x = common dso_local global i128 0
 @y = common dso_local global i128 0
@@ -116,3 +117,53 @@ define void @test7() {
   store volatile i128 %tmp, ptr getelementptr (i8, ptr @y, i64 503)
   ret void
 }
+
+define i128 @load_nonvol(i32, i32, ptr %p) {
+; CHECK-LABEL: load_nonvol:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ldp x0, x1, [x2]
+; CHECK-NEXT:    ret
+entry:
+  %l = load i128, ptr %p, align 16
+  ret i128 %l
+}
+
+define i128 @load_vol(i32, i32, ptr %p) {
+; CHECK-LE-LABEL: load_vol:
+; CHECK-LE:       // %bb.0: // %entry
+; CHECK-LE-NEXT:    ldp x0, x1, [x2]
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: load_vol:
+; CHECK-BE:       // %bb.0: // %entry
+; CHECK-BE-NEXT:    ldp x1, x0, [x2]
+; CHECK-BE-NEXT:    ret
+entry:
+  %l = load volatile i128, ptr %p, align 16
+  ret i128 %l
+}
+
+define void @store_nonvol(i128 %a, ptr %p) {
+; CHECK-LABEL: store_nonvol:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    stp x0, x1, [x2]
+; CHECK-NEXT:    ret
+entry:
+  store i128 %a, ptr %p, align 16
+  ret void
+}
+
+define void @loadstore_vol(i128 %a, ptr %p) {
+; CHECK-LE-LABEL: loadstore_vol:
+; CHECK-LE:       // %bb.0: // %entry
+; CHECK-LE-NEXT:    stp x0, x1, [x2]
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: loadstore_vol:
+; CHECK-BE:       // %bb.0: // %entry
+; CHECK-BE-NEXT:    stp x1, x0, [x2]
+; CHECK-BE-NEXT:    ret
+entry:
+  store volatile i128 %a, ptr %p, align 16
+  ret void
+}