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llvm-reduce: Don't set generic instruction operands to undef
The intention is that these should never have undef operands. It turns out the restriction the verifier enforces is too lax. The verifier enforces that registers without a register class cannot be undef, but it's valid to use a register with a register class and type. The verifier needs to change to be based on the opcode.
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25 changes: 25 additions & 0 deletions
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llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
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Original file line number | Diff line number | Diff line change |
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# REQUIRES: amdgpu-registered-target | ||
# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log | ||
# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t | ||
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# Generic instructions should not have undef set on operands | ||
# CHECK-INTERESTINGNESS: G_ADD | ||
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# RESULT: %1:vreg_64(s64) = IMPLICIT_DEF | ||
# RESULT: %add:_(s64) = G_ADD %1, %1 | ||
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--- | ||
name: func | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3 | ||
%0:vgpr(s32) = G_IMPLICIT_DEF | ||
%1:vreg_64(s64) = IMPLICIT_DEF | ||
%add:_(s64) = G_ADD %1, %1 | ||
%ptr:_(p1) = G_IMPLICIT_DEF | ||
G_STORE %0(s32), %ptr(p1) :: (store (s32), addrspace 1) | ||
S_ENDPGM 0, implicit %add(s64), implicit %1(s64) | ||
... |
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