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Revert "[flang][openacc] Add missing piece to translate to LLVM IR di…
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…alect"

This reverts commit 03289dc.
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clementval committed Apr 10, 2023
1 parent 132f1d3 commit cc0a004
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Showing 6 changed files with 3 additions and 75 deletions.
1 change: 0 additions & 1 deletion flang/lib/Optimizer/CodeGen/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,6 @@ add_flang_library(FIRCodeGen
MLIRMathToFuncs
MLIRMathToLLVM
MLIRMathToLibm
MLIROpenACCToLLVM
MLIROpenMPToLLVM
MLIRBuiltinToLLVMIRTranslation
MLIRLLVMToLLVMIRTranslation
Expand Down
33 changes: 2 additions & 31 deletions flang/lib/Optimizer/CodeGen/CodeGen.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -31,11 +31,8 @@
#include "mlir/Conversion/MathToFuncs/MathToFuncs.h"
#include "mlir/Conversion/MathToLLVM/MathToLLVM.h"
#include "mlir/Conversion/MathToLibm/MathToLibm.h"
#include "mlir/Conversion/OpenACCToLLVM/ConvertOpenACCToLLVM.h"
#include "mlir/Conversion/OpenMPToLLVM/ConvertOpenMPToLLVM.h"
#include "mlir/Conversion/ReconcileUnrealizedCasts/ReconcileUnrealizedCasts.h"
#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
#include "mlir/Dialect/OpenACC/OpenACC.h"
#include "mlir/Dialect/OpenMP/OpenMPDialect.h"
#include "mlir/IR/BuiltinTypes.h"
#include "mlir/IR/Matchers.h"
Expand Down Expand Up @@ -3643,29 +3640,6 @@ struct MustBeDeadConversion : public FIROpConversion<FromOp> {
}
};

struct UnrealizedConversionCastOpConversion
: public FIROpConversion<mlir::UnrealizedConversionCastOp> {
using FIROpConversion::FIROpConversion;

mlir::LogicalResult
matchAndRewrite(mlir::UnrealizedConversionCastOp op, OpAdaptor adaptor,
mlir::ConversionPatternRewriter &rewriter) const override {
assert(op.getOutputs().getTypes().size() == 1 && "expect a single type");
mlir::Type convertedType = convertType(op.getOutputs().getTypes()[0]);
if (convertedType == adaptor.getInputs().getTypes()[0]) {
rewriter.replaceOp(op, adaptor.getInputs());
return mlir::success();
}

convertedType = adaptor.getInputs().getTypes()[0];
if (convertedType == op.getOutputs().getType()[0]) {
rewriter.replaceOp(op, adaptor.getInputs());
return mlir::success();
}
return mlir::failure();
}
};

struct ShapeOpConversion : public MustBeDeadConversion<fir::ShapeOp> {
using MustBeDeadConversion::MustBeDeadConversion;
};
Expand Down Expand Up @@ -3788,11 +3762,9 @@ class FIRToLLVMLowering
SliceOpConversion, StoreOpConversion, StringLitOpConversion,
SubcOpConversion, TypeDescOpConversion, UnboxCharOpConversion,
UnboxProcOpConversion, UndefOpConversion, UnreachableOpConversion,
UnrealizedConversionCastOpConversion, XArrayCoorOpConversion,
XEmboxOpConversion, XReboxOpConversion, ZeroOpConversion>(typeConverter,
options);
XArrayCoorOpConversion, XEmboxOpConversion, XReboxOpConversion,
ZeroOpConversion>(typeConverter, options);
mlir::populateFuncToLLVMConversionPatterns(typeConverter, pattern);
mlir::populateOpenACCToLLVMConversionPatterns(typeConverter, pattern);
mlir::populateOpenMPToLLVMConversionPatterns(typeConverter, pattern);
mlir::arith::populateArithToLLVMConversionPatterns(typeConverter, pattern);
mlir::cf::populateControlFlowToLLVMConversionPatterns(typeConverter,
Expand All @@ -3809,7 +3781,6 @@ class FIRToLLVMLowering
// legalize conversion of OpenMP operations without regions.
mlir::configureOpenMPToLLVMConversionLegality(target, typeConverter);
target.addLegalDialect<mlir::omp::OpenMPDialect>();
target.addLegalDialect<mlir::acc::OpenACCDialect>();

// required NOPs for applying a full conversion
target.addLegalOp<mlir::ModuleOp>();
Expand Down
1 change: 0 additions & 1 deletion flang/lib/Optimizer/Support/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,6 @@ add_flang_library(FIRSupport
LINK_LIBS
${dialect_libs}
MLIRBuiltinToLLVMIRTranslation
MLIROpenACCToLLVMIRTranslation
MLIROpenMPToLLVMIRTranslation
MLIRLLVMToLLVMIRTranslation
MLIRTargetLLVMIRExport
Expand Down
3 changes: 0 additions & 3 deletions flang/lib/Optimizer/Support/InitFIR.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,10 @@
#include "flang/Optimizer/Support/InitFIR.h"
#include "mlir/Target/LLVMIR/Dialect/Builtin/BuiltinToLLVMIRTranslation.h"
#include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h"
#include "mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h"
#include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h"

void fir::support::registerLLVMTranslation(mlir::MLIRContext &context) {
mlir::DialectRegistry registry;
// Register OpenACC dialect interface here as well.
registerOpenACCDialectTranslation(registry);
// Register OpenMP dialect interface here as well.
registerOpenMPDialectTranslation(registry);
// Register LLVM-IR dialect interface.
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,7 @@ void OpenACCDataOperandConversion::runOnOperation() {
ConversionTarget target(*context);
target.addLegalDialect<fir::FIROpsDialect>();
target.addLegalDialect<LLVM::LLVMDialect>();
target.addLegalOp<mlir::UnrealizedConversionCastOp>();
target.addLegalOp<UnrealizedConversionCastOp>();

auto allDataOperandsAreConverted = [](ValueRange operands) {
for (Value operand : operands) {
Expand Down
38 changes: 0 additions & 38 deletions flang/test/Transforms/OpenACC/convert-data-operands-to-llvmir.fir
Original file line number Diff line number Diff line change
@@ -1,10 +1,4 @@
// RUN: fir-opt -fir-openacc-data-operand-conversion='use-opaque-pointers=1' -split-input-file %s | FileCheck %s
// RUN: fir-opt -fir-openacc-data-operand-conversion='use-opaque-pointers=1' -split-input-file %s | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefix=LLVMIR

fir.global internal @_QFEa : !fir.array<10xf32> {
%0 = fir.undefined !fir.array<10xf32>
fir.has_value %0 : !fir.array<10xf32>
}

func.func @_QQsub1() attributes {fir.bindc_name = "arr"} {
%0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
Expand All @@ -19,17 +13,8 @@ func.func @_QQsub1() attributes {fir.bindc_name = "arr"} {
// CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
// CHECK: acc.data copy(%[[CAST]] : !llvm.ptr<array<10 x f32>>)

// LLVMIR-LABEL: llvm.func @_QQsub1() attributes {fir.bindc_name = "arr"} {
// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
// LLVMIR: acc.data copy(%[[ADDR]] : !llvm.ptr<array<10 x f32>>) {

// -----

fir.global internal @_QFEa : !fir.array<10xf32> {
%0 = fir.undefined !fir.array<10xf32>
fir.has_value %0 : !fir.array<10xf32>
}

func.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
%0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
acc.enter_data copyin(%0 : !fir.ref<!fir.array<10xf32>>)
Expand All @@ -44,18 +29,8 @@ func.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
// CHECK: %[[CAST1:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
// CHECK: acc.exit_data copyout(%[[CAST1]] : !llvm.ptr<array<10 x f32>>)

// LLVMIR-LABEL: llvm.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
// LLVMIR: acc.enter_data copyin(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)
// LLVMIR: acc.exit_data copyout(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)

// -----

fir.global internal @_QFEa : !fir.array<10xf32> {
%0 = fir.undefined !fir.array<10xf32>
fir.has_value %0 : !fir.array<10xf32>
}

func.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
%0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
acc.update device(%0 : !fir.ref<!fir.array<10xf32>>)
Expand All @@ -67,17 +42,8 @@ func.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
// CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
// CHECK: acc.update device(%[[CAST]] : !llvm.ptr<array<10 x f32>>)

// LLVMIR-LABEL: llvm.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
// LLVMIR: acc.update device(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)

// -----

fir.global internal @_QFEa : !fir.array<10xf32> {
%0 = fir.undefined !fir.array<10xf32>
fir.has_value %0 : !fir.array<10xf32>
}

func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
%0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
%1 = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFEi"}
Expand Down Expand Up @@ -116,7 +82,3 @@ func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
// CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
// CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
// CHECK: acc.parallel copyin(%[[CAST]]: !llvm.ptr<array<10 x f32>>) {

// LLVMIR-LABEL: llvm.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
// LLVMIR: acc.parallel copyin(%[[ADDR]]: !llvm.ptr<array<10 x f32>>) {

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