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[AMDGPU][MC][NFC] MUBUF/MTBUF code cleanup
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Refactor code to reduce code duplication and improve maintainability.

- Extract BUF_Pseudo common base class
- Refactor getMUBUFInsDA
- Refactor getMUBUFAtomicInsDA
- Refactor getMTBUFInsDA
- Refactor getMUBUFAsmOps
- Refactor getMTBUFAsmOps

Differential Revision: https://reviews.llvm.org/D140410
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@piotrAMD
piotrAMD committed Dec 21, 2022
1 parent 1118ee0 commit cce3cd2
Showing 1 changed file with 65 additions and 105 deletions.
170 changes: 65 additions & 105 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
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Expand Up @@ -40,18 +40,12 @@ class MTBUFAddr64Table <bit is_addr64, string Name> {
string OpName = Name;
}


//===----------------------------------------------------------------------===//
// MTBUF classes
// BUF class (base class for MTBUF and MUBUF pseudos)
//===----------------------------------------------------------------------===//

class MTBUFGetBaseOpcode<string Op> {
string ret = !subst("FORMAT_XY", "FORMAT_X",
!subst("FORMAT_XYZ", "FORMAT_X",
!subst("FORMAT_XYZW", "FORMAT_X", Op)));
}


class MTBUF_Pseudo <string opName, dag outs, dag ins,
class BUF_Pseudo <string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
InstSI<outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
Expand All @@ -65,21 +59,22 @@ class MTBUF_Pseudo <string opName, dag outs, dag ins,
string AsmOperands = asmOps;

Instruction Opcode = !cast<Instruction>(NAME);
Instruction BaseOpcode = !cast<Instruction>(MTBUFGetBaseOpcode<NAME>.ret);


let VM_CNT = 1;
let EXP_CNT = 1;
let MTBUF = 1;

let Uses = [EXEC];
let hasSideEffects = 0;
let SchedRW = [WriteVMEM];

let AsmMatchConverter = "cvtMtbuf";


bits<1> offen = 0;
bits<1> idxen = 0;
bits<1> addr64 = 0;
bits<1> has_vdata = 1;
bits<1> lds = 0;
bits<1> has_vdata = !not(lds);
bits<1> has_vaddr = 1;
bits<1> has_glc = 1;
bits<1> has_dlc = 1;
Expand All @@ -93,6 +88,29 @@ class MTBUF_Pseudo <string opName, dag outs, dag ins,
bits<4> elements = 0;
bits<1> has_sccb = 1;
bits<1> sccb_value = 0;
bits<1> IsBufferInv = 0;
}



//===----------------------------------------------------------------------===//
// MTBUF classes
//===----------------------------------------------------------------------===//

class MTBUFGetBaseOpcode<string Op> {
string ret = !subst("FORMAT_XY", "FORMAT_X",
!subst("FORMAT_XYZ", "FORMAT_X",
!subst("FORMAT_XYZW", "FORMAT_X", Op)));
}


class MTBUF_Pseudo <string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
BUF_Pseudo <opName, outs, ins, asmOps, pattern> {

Instruction BaseOpcode = !cast<Instruction>(MTBUFGetBaseOpcode<NAME>.ret);
let MTBUF = 1;
let AsmMatchConverter = "cvtMtbuf";
}

class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
Expand Down Expand Up @@ -139,23 +157,13 @@ class getMTBUFInsDA<list<RegisterClass> vdataList,
RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
RegisterOperand vdata_op = getLdStRegisterOperand<vdataClass>.ret;
dag InsNoData = !if(!empty(vaddrList),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, FORMAT:$format, CPol:$cpol, SWZ:$swz),
(ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, FORMAT:$format, CPol:$cpol, SWZ:$swz)
);
dag InsData = !if(!empty(vaddrList),
(ins vdata_op:$vdata, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol,
SWZ:$swz),
(ins vdata_op:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol,
SWZ:$swz)
);
dag ret = !if(!empty(vdataList), InsNoData, InsData);

dag NonVaddrInputs = (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol, SWZ:$swz);
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddrClass:$vaddr), NonVaddrInputs));
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
}


class getMTBUFIns<int addrKind, list<RegisterClass> vdataList=[]> {
dag ret =
!if(!eq(addrKind, BUFAddrKind.Offset), getMTBUFInsDA<vdataList>.ret,
Expand All @@ -178,7 +186,7 @@ class getMTBUFAsmOps<int addrKind> {
!if(!eq(addrKind, BUFAddrKind.Addr64),
"$vaddr, $srsrc,$format $soffset addr64",
"")))));
string ret = Pfx # "$offset";
string ret = " $vdata, " # Pfx # "$offset$cpol$swz";
}

class MTBUF_SetupAddr<int addrKind> {
Expand All @@ -203,7 +211,7 @@ class MTBUF_Load_Pseudo <string opName,
: MTBUF_Pseudo<opName,
(outs getLdStRegisterOperand<vdataClass>.ret:$vdata),
getMTBUFIns<addrKindCopy>.ret,
" $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$cpol$swz",
getMTBUFAsmOps<addrKindCopy>.ret,
pattern>,
MTBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
Expand Down Expand Up @@ -244,7 +252,7 @@ class MTBUF_Store_Pseudo <string opName,
: MTBUF_Pseudo<opName,
(outs),
getMTBUFIns<addrKindCopy, [vdataClassCopy]>.ret,
" $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$cpol$swz",
getMTBUFAsmOps<addrKindCopy>.ret,
pattern>,
MTBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
Expand Down Expand Up @@ -287,48 +295,11 @@ class MUBUFGetBaseOpcode<string Op> {

class MUBUF_Pseudo <string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
InstSI<outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {

let isPseudo = 1;
let isCodeGenOnly = 1;
let Size = 8;
let UseNamedOperandTable = 1;
BUF_Pseudo <opName, outs, ins, asmOps, pattern> {

string Mnemonic = opName;
string AsmOperands = asmOps;

Instruction Opcode = !cast<Instruction>(NAME);
Instruction BaseOpcode = !cast<Instruction>(MUBUFGetBaseOpcode<NAME>.ret);

let VM_CNT = 1;
let EXP_CNT = 1;
let MUBUF = 1;
let Uses = [EXEC];
let hasSideEffects = 0;
let SchedRW = [WriteVMEM];

let AsmMatchConverter = "cvtMubuf";

bits<1> offen = 0;
bits<1> idxen = 0;
bits<1> addr64 = 0;
bits<1> lds = 0;
bits<1> has_vdata = !not(lds);
bits<1> has_vaddr = 1;
bits<1> has_glc = 1;
bits<1> has_dlc = 1;
bits<1> glc_value = 0; // the value for glc if no such operand
bits<1> dlc_value = 0; // the value for dlc if no such operand
bits<1> has_srsrc = 1;
bits<1> has_soffset = 1;
bits<1> has_offset = 1;
bits<1> has_slc = 1;
bits<1> tfe = ?;
bits<4> elements = 0;
bits<1> has_sccb = 1;
bits<1> sccb_value = 0;
bits<1> IsBufferInv = 0;
}

class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
Expand Down Expand Up @@ -369,7 +340,6 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
bits<1> acc = !if(ps.has_vdata, vdata{9}, !if(ps.lds, ?, 0));
}


// For cache invalidation instructions.
class MUBUF_Invalidate <string opName, SDPatternOperator node = null_frag> :
MUBUF_Pseudo<opName, (outs), (ins), "", [(node)]> {
Expand Down Expand Up @@ -416,19 +386,10 @@ class getMUBUFInsDA<list<RegisterClass> vdataList,
RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
RegisterOperand vdata_op = getLdStVDataRegisterOperand<vdataClass, isTFE>.ret;
dag InsNoData = !if(!empty(vaddrList),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, CPol_0:$cpol),
(ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, CPol_0:$cpol)
);
dag InsData = !if(!empty(vaddrList),
(ins vdata_op:$vdata, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, CPol_0:$cpol),
(ins vdata_op:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, CPol_0:$cpol)
);
dag ret = !con(!if(!empty(vdataList), InsNoData, InsData), (ins SWZ_0:$swz));

dag NonVaddrInputs = (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol_0:$cpol, SWZ_0:$swz);
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddrClass:$vaddr), NonVaddrInputs));
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
}

class getMUBUFElements<ValueType vt> {
Expand Down Expand Up @@ -460,15 +421,22 @@ class getMUBUFIns<int addrKind, list<RegisterClass> vdataList, bit isTFE> {
(ins))))));
}

class getMUBUFAsmOps<int addrKind> {
string Pfx =
class getMUBUFAsmOps<int addrKind, bit noVdata = 0, bit isLds = 0, bit isTFE = 0, bit isSwz = 0> {
string Vdata = !if(noVdata, " ", " $vdata, ");
string Lds = !if(isLds, " lds", "");
string TFE = !if(isTFE, " tfe", "");
string MainArgs =
!if(!eq(addrKind, BUFAddrKind.Offset), "off, $srsrc, $soffset",
!if(!eq(addrKind, BUFAddrKind.OffEn), "$vaddr, $srsrc, $soffset offen",
!if(!eq(addrKind, BUFAddrKind.IdxEn), "$vaddr, $srsrc, $soffset idxen",
!if(!eq(addrKind, BUFAddrKind.BothEn), "$vaddr, $srsrc, $soffset idxen offen",
!if(!eq(addrKind, BUFAddrKind.Addr64), "$vaddr, $srsrc, $soffset addr64",
"")))));
string ret = Pfx # "$offset";
string Offset = "$offset";
string OtherArgs = "$cpol";
string Swz = !if(isSwz, "$swz", "");

string ret = Vdata # MainArgs # Offset # OtherArgs # Lds # TFE # Swz;
}

class MUBUF_SetupAddr<int addrKind> {
Expand Down Expand Up @@ -499,8 +467,7 @@ class MUBUF_Load_Pseudo <string opName,
!if(!or(isLds, isLdsOpc), (outs), (outs vdata_op:$vdata)),
!con(getMUBUFIns<addrKindCopy, [], isTFE>.ret,
!if(HasTiedDest, (ins vdata_op:$vdata_in), (ins))),
!if(!or(isLds, isLdsOpc), " ", " $vdata, ") # getMUBUFAsmOps<addrKindCopy>.ret # "$cpol" #
!if(isLds, " lds", "") # !if(isTFE, " tfe", "") # "$swz",
getMUBUFAsmOps<addrKindCopy, !or(isLds, isLdsOpc), isLds, isTFE, 1>.ret,
pattern>,
MUBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # !if(isLds, "_lds", "") # !if(isTFE, "_tfe", "") #
Expand Down Expand Up @@ -595,8 +562,7 @@ class MUBUF_Store_Pseudo <string opName,
: MUBUF_Pseudo<opName,
(outs),
getMUBUFIns<addrKindCopy, [getVregSrcForVT<store_vt>.ret], isTFE>.ret,
" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$cpol" #
!if(isTFE, " tfe", "") # "$swz",
getMUBUFAsmOps<addrKindCopy, 0, 0, isTFE, 1>.ret,
pattern>,
MUBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # "_" # !if(isTFE, "_tfe", "") #
Expand Down Expand Up @@ -663,19 +629,13 @@ class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in,
list<RegisterClass> vaddrList=[]> {
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
RegisterOperand vdata_op = getLdStRegisterOperand<vdataClass>.ret;
dag ret = !if(vdata_in,
!if(!empty(vaddrList),
(ins vdata_op:$vdata_in,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol_GLC1:$cpol),
(ins vdata_op:$vdata_in, vaddrClass:$vaddr,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol_GLC1:$cpol)
),
!if(!empty(vaddrList),
(ins vdata_op:$vdata,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol_0:$cpol),
(ins vdata_op:$vdata, vaddrClass:$vaddr,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol_0:$cpol)
));

dag VData = !if(vdata_in, (ins vdata_op:$vdata_in), (ins vdata_op:$vdata));
dag Data = !if(!empty(vaddrList), VData, !con(VData, (ins vaddrClass:$vaddr)));
dag MainInputs = (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset);
dag CPol = !if(vdata_in, (ins CPol_GLC1:$cpol), (ins CPol_0:$cpol));

dag ret = !con(Data, !con(MainInputs, CPol));
}

class getMUBUFAtomicIns<int addrKind,
Expand Down Expand Up @@ -728,7 +688,7 @@ class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind,
: MUBUF_Atomic_Pseudo<opName, addrKindCopy,
(outs),
getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 0>.ret,
" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$cpol",
getMUBUFAsmOps<addrKindCopy>.ret,
pattern>,
AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 0> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
Expand All @@ -748,7 +708,7 @@ class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
: MUBUF_Atomic_Pseudo<opName, addrKindCopy,
(outs vdata_op:$vdata),
getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 1>.ret,
" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$cpol",
getMUBUFAsmOps<addrKindCopy>.ret,
pattern>,
AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 1> {
let PseudoInstr = opName # "_rtn_" # getAddrName<addrKindCopy>.ret;
Expand Down

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