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Revert "[AArch64] Add hex comments to mov-imm spellings in the InstPr…
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…inter"

This reverts commit 1def314.
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@jroelofs
jroelofs committed Mar 15, 2023
1 parent 1def314 commit cdee83b
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Showing 2 changed files with 28 additions and 36 deletions.
32 changes: 12 additions & 20 deletions llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
View file
Expand Up @@ -282,23 +282,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
return;
}

auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
int64_t SExtVal = SignExtend64(Value, RegWidth);
O << "\tmov\t";
printRegName(O, MI->getOperand(0).getReg());
O << ", " << markup("<imm:") << "#"
<< formatImm(SExtVal) << markup(">");
if (CommentStream) {
// Do the opposite to that used for instruction operands.
if (getPrintImmHex())
*CommentStream << '=' << formatDec(SExtVal) << '\n';
else {
uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
*CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
}
}
};

// MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
// domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
// MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
Expand All @@ -312,7 +295,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,

if (AArch64_AM::isMOVZMovAlias(Value, Shift,
Opcode == AArch64::MOVZXi ? 64 : 32)) {
PrintMovImm(Value, RegWidth);
O << "\tmov\t";
printRegName(O, MI->getOperand(0).getReg());
O << ", " << markup("<imm:") << "#"
<< formatImm(SignExtend64(Value, RegWidth)) << markup(">");
return;
}
}
Expand All @@ -326,7 +312,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
Value = Value & 0xffffffff;

if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
PrintMovImm(Value, RegWidth);
O << "\tmov\t";
printRegName(O, MI->getOperand(0).getReg());
O << ", " << markup("<imm:") << "#"
<< formatImm(SignExtend64(Value, RegWidth)) << markup(">");
return;
}
}
Expand All @@ -339,7 +328,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
uint64_t Value = AArch64_AM::decodeLogicalImmediate(
MI->getOperand(2).getImm(), RegWidth);
if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
PrintMovImm(Value, RegWidth);
O << "\tmov\t";
printRegName(O, MI->getOperand(0).getReg());
O << ", " << markup("<imm:") << "#"
<< formatImm(SignExtend64(Value, RegWidth)) << markup(">");
return;
}
}
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AArch64/movw-consts.ll
View file
Expand Up @@ -13,55 +13,55 @@ define i64 @test0() {
define i64 @test1() {
; CHECK-LABEL: test1:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w0, #1 ; =0x1
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: ret
ret i64 1
}

define i64 @test2() {
; CHECK-LABEL: test2:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w0, #65535 ; =0xffff
; CHECK-NEXT: mov w0, #65535
; CHECK-NEXT: ret
ret i64 65535
}

define i64 @test3() {
; CHECK-LABEL: test3:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w0, #65536 ; =0x10000
; CHECK-NEXT: mov w0, #65536
; CHECK-NEXT: ret
ret i64 65536
}

define i64 @test4() {
; CHECK-LABEL: test4:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w0, #-65536 ; =0xffff0000
; CHECK-NEXT: mov w0, #-65536
; CHECK-NEXT: ret
ret i64 4294901760
}

define i64 @test5() {
; CHECK-LABEL: test5:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x0, #4294967296 ; =0x100000000
; CHECK-NEXT: mov x0, #4294967296
; CHECK-NEXT: ret
ret i64 4294967296
}

define i64 @test6() {
; CHECK-LABEL: test6:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x0, #281470681743360 ; =0xffff00000000
; CHECK-NEXT: mov x0, #281470681743360
; CHECK-NEXT: ret
ret i64 281470681743360
}

define i64 @test7() {
; CHECK-LABEL: test7:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x0, #281474976710656 ; =0x1000000000000
; CHECK-NEXT: mov x0, #281474976710656
; CHECK-NEXT: ret
ret i64 281474976710656
}
Expand All @@ -71,23 +71,23 @@ define i64 @test7() {
define i64 @test8() {
; CHECK-LABEL: test8:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w0, #-60876 ; =0xffff1234
; CHECK-NEXT: mov w0, #-60876
; CHECK-NEXT: ret
ret i64 4294906420
}

define i64 @test9() {
; CHECK-LABEL: test9:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x0, #-1 ; =0xffffffffffffffff
; CHECK-NEXT: mov x0, #-1
; CHECK-NEXT: ret
ret i64 -1
}

define i64 @test10() {
; CHECK-LABEL: test10:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x0, #-3989504001 ; =0xffffffff1234ffff
; CHECK-NEXT: mov x0, #-3989504001
; CHECK-NEXT: ret
ret i64 18446744069720047615
}
Expand All @@ -110,7 +110,7 @@ define void @test12() {
; CHECK-LABEL: test12:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
; CHECK-NEXT: mov w9, #1 ; =0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 1, ptr @var32
Expand All @@ -121,7 +121,7 @@ define void @test13() {
; CHECK-LABEL: test13:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
; CHECK-NEXT: mov w9, #65535 ; =0xffff
; CHECK-NEXT: mov w9, #65535
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 65535, ptr @var32
Expand All @@ -132,7 +132,7 @@ define void @test14() {
; CHECK-LABEL: test14:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
; CHECK-NEXT: mov w9, #65536 ; =0x10000
; CHECK-NEXT: mov w9, #65536
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 65536, ptr @var32
Expand All @@ -143,7 +143,7 @@ define void @test15() {
; CHECK-LABEL: test15:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
; CHECK-NEXT: mov w9, #-65536 ; =0xffff0000
; CHECK-NEXT: mov w9, #-65536
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 4294901760, ptr @var32
Expand All @@ -154,7 +154,7 @@ define void @test16() {
; CHECK-LABEL: test16:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
; CHECK-NEXT: mov w9, #-1 ; =0xffffffff
; CHECK-NEXT: mov w9, #-1
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 -1, ptr @var32
Expand All @@ -164,7 +164,7 @@ define void @test16() {
define i64 @test17() {
; CHECK-LABEL: test17:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x0, #-3 ; =0xfffffffffffffffd
; CHECK-NEXT: mov x0, #-3
; CHECK-NEXT: ret

; Mustn't MOVN w0 here.
Expand Down

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