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[AArch64] Regenerate more tests. NFC
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Also includes some adjustments for asm.py to handle updating more cases
successfully.
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@davemgreen
davemgreen committed Jul 3, 2022
1 parent 53dc0f1 commit d100a30
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Showing 8 changed files with 754 additions and 468 deletions.
68 changes: 37 additions & 31 deletions llvm/test/CodeGen/AArch64/global-merge-group-by-use.ll
View file
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-apple-ios -asm-verbose=false \
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-ios \
; RUN: -aarch64-enable-collect-loh=false -aarch64-enable-global-merge \
; RUN: -global-merge-group-by-use -global-merge-ignore-single-use=false %s \
; RUN: -o - | FileCheck %s
Expand All @@ -11,12 +12,13 @@
@m1 = internal global i32 0, align 4
@n1 = internal global i32 0, align 4

; CHECK-LABEL: f1:
define void @f1(i32 %a1, i32 %a2) #0 {
; CHECK-NEXT: adrp x8, [[SET1:__MergedGlobals.[0-9]*]]@PAGE
; CHECK-NEXT: add x8, x8, [[SET1]]@PAGEOFF
; CHECK-NEXT: stp w0, w1, [x8]
; CHECK-NEXT: ret
; CHECK-LABEL: f1:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, __MergedGlobals.2@PAGE
; CHECK-NEXT: add x8, x8, __MergedGlobals.2@PAGEOFF
; CHECK-NEXT: stp w0, w1, [x8]
; CHECK-NEXT: ret
store i32 %a1, i32* @m1, align 4
store i32 %a2, i32* @n1, align 4
ret void
Expand All @@ -26,13 +28,14 @@ define void @f1(i32 %a1, i32 %a2) #0 {
@n2 = internal global i32 0, align 4
@o2 = internal global i32 0, align 4

; CHECK-LABEL: f2:
define void @f2(i32 %a1, i32 %a2, i32 %a3) #0 {
; CHECK-NEXT: adrp x8, [[SET2:__MergedGlobals.[0-9]*]]@PAGE
; CHECK-NEXT: add x8, x8, [[SET2]]@PAGEOFF
; CHECK-NEXT: stp w0, w1, [x8]
; CHECK-NEXT: str w2, [x8, #8]
; CHECK-NEXT: ret
; CHECK-LABEL: f2:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, __MergedGlobals.1@PAGE
; CHECK-NEXT: add x8, x8, __MergedGlobals.1@PAGEOFF
; CHECK-NEXT: stp w0, w1, [x8]
; CHECK-NEXT: str w2, [x8, #8]
; CHECK-NEXT: ret
store i32 %a1, i32* @m2, align 4
store i32 %a2, i32* @n2, align 4
store i32 %a3, i32* @o2, align 4
Expand All @@ -46,13 +49,14 @@ define void @f2(i32 %a1, i32 %a2, i32 %a3) #0 {
@m3 = internal global i32 0, align 4
@n3 = internal global i32 0, align 4

; CHECK-LABEL: f3:
define void @f3(i32 %a1, i32 %a2) #0 {
; CHECK-NEXT: adrp x8, _m3@PAGE
; CHECK-NEXT: adrp x9, [[SET3:__MergedGlobals[0-9]*]]@PAGE
; CHECK-NEXT: str w0, [x8, _m3@PAGEOFF]
; CHECK-NEXT: str w1, [x9, [[SET3]]@PAGEOFF]
; CHECK-NEXT: ret
; CHECK-LABEL: f3:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _m3@PAGE
; CHECK-NEXT: adrp x9, __MergedGlobals@PAGE
; CHECK-NEXT: str w0, [x8, _m3@PAGEOFF]
; CHECK-NEXT: str w1, [x9, __MergedGlobals@PAGEOFF]
; CHECK-NEXT: ret
store i32 %a1, i32* @m3, align 4
store i32 %a2, i32* @n3, align 4
ret void
Expand All @@ -61,13 +65,14 @@ define void @f3(i32 %a1, i32 %a2) #0 {
@m4 = internal global i32 0, align 4
@n4 = internal global i32 0, align 4

; CHECK-LABEL: f4:
define void @f4(i32 %a1, i32 %a2, i32 %a3) #0 {
; CHECK-NEXT: adrp x8, [[SET3]]@PAGE
; CHECK-NEXT: add x8, x8, [[SET3]]@PAGEOFF
; CHECK-NEXT: stp w0, w1, [x8, #4]
; CHECK-NEXT: str w2, [x8]
; CHECK-NEXT: ret
; CHECK-LABEL: f4:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, __MergedGlobals@PAGE
; CHECK-NEXT: add x8, x8, __MergedGlobals@PAGEOFF
; CHECK-NEXT: stp w0, w1, [x8, #4]
; CHECK-NEXT: str w2, [x8]
; CHECK-NEXT: ret
store i32 %a1, i32* @m4, align 4
store i32 %a2, i32* @n4, align 4
store i32 %a3, i32* @n3, align 4
Expand All @@ -77,19 +82,20 @@ define void @f4(i32 %a1, i32 %a2, i32 %a3) #0 {
; Finally, check that we don't do anything with one-element global sets.
@o5 = internal global i32 0, align 4

; CHECK-LABEL: f5:
define void @f5(i32 %a1) #0 {
; CHECK-NEXT: adrp x8, _o5@PAGE
; CHECK-NEXT: str w0, [x8, _o5@PAGEOFF]
; CHECK-NEXT: ret
; CHECK-LABEL: f5:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _o5@PAGE
; CHECK-NEXT: str w0, [x8, _o5@PAGEOFF]
; CHECK-NEXT: ret
store i32 %a1, i32* @o5, align 4
ret void
}

; CHECK-DAG: .zerofill __DATA,__bss,_o5,4,2

; CHECK-DAG: .zerofill __DATA,__bss,[[SET1]],8,2
; CHECK-DAG: .zerofill __DATA,__bss,[[SET2]],12,2
; CHECK-DAG: .zerofill __DATA,__bss,[[SET3]],12,2
; CHECK-DAG: .zerofill __DATA,__bss,__MergedGlobals.2,8,2
; CHECK-DAG: .zerofill __DATA,__bss,__MergedGlobals.1,12,2
; CHECK-DAG: .zerofill __DATA,__bss,__MergedGlobals,12,2

attributes #0 = { nounwind }
36 changes: 20 additions & 16 deletions llvm/test/CodeGen/AArch64/sve-fix-length-and-combine-512.ll
View file
@@ -1,15 +1,17 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=512 -o - -asm-verbose=0 < %s | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=512 -o - < %s | FileCheck %s

; CHECK-LABEL: vls_sve_and_64xi8:
; CHECK-NEXT: adrp x[[ONE:[0-9]+]], .LCPI0_0
; CHECK-NEXT: add x[[TWO:[0-9]+]], x[[ONE]], :lo12:.LCPI0_0
; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-NEXT: ld1b { z1.b }, p0/z, [x[[TWO]]]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: st1b { z0.b }, p0, [x1]
; CHECK-NEXT: ret
define void @vls_sve_and_64xi8(<64 x i8>* %ap, <64 x i8>* %out) nounwind {
; CHECK-LABEL: vls_sve_and_64xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI0_0
; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-NEXT: ld1b { z1.b }, p0/z, [x8]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: st1b { z0.b }, p0, [x1]
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %ap
%b = and <64 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
Expand All @@ -19,18 +21,20 @@ define void @vls_sve_and_64xi8(<64 x i8>* %ap, <64 x i8>* %out) nounwind {
ret void
}

; CHECK-LABEL: vls_sve_and_16xi8:
; CHECK-NEXT: bic v0.8h, #255
; CHECK-NEXT: ret
define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b, <16 x i8>* %out) nounwind {
; CHECK-LABEL: vls_sve_and_16xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: bic v0.8h, #255
; CHECK-NEXT: ret
%c = and <16 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <16 x i8> %c
}

; CHECK-LABEL: vls_sve_and_8xi8:
; CHECK-NEXT: bic v0.4h, #255
; CHECK-NEXT: ret
define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b, <8 x i8>* %out) nounwind {
; CHECK-LABEL: vls_sve_and_8xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: bic v0.4h, #255
; CHECK-NEXT: ret
%c = and <8 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %c
}
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