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[AMDGPU] Tune scheduler on GFX10 and GFX11 for regions with spilling
Unlike older ASICs GFX10+ have a lot of VGPRs. Therefore, it is possible to achieve high occupancy even with all or almost all addressable VGPRs used. Our scheduler was never tuned for this scenario. The VGPR Critical Limit threshold always comes very high, even if maximum occupancy is targeted. For example on gfx1100 it is set to 192 registers even with the requested occupancy 16. As a result scheduler starts prioritizing register pressure reduction very late and we easily end up spilling. This patch makes VGPR critical limit similar to what we would have on pre-gfx10 targets with much more limited VGPR budget while still trying to maintain occupancy as it does now. Pre-gfx10 ASICs shall not be affected as the limit shall be the same as before, and on gfx10+ it shall only affect regions where we have to spill. Fixes: SWDEV-377300 Differential Revision: https://reviews.llvm.org/D141876
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