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[X86] Enable reassociation for ADD instructions
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ADD is an associative and commutative operation, so we can do reassociation for it.

Differential Revision: https://reviews.llvm.org/D136396
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@weiguozhi
weiguozhi committed Oct 26, 2022
1 parent e5d9e80 commit d24c93c
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Showing 58 changed files with 5,200 additions and 5,231 deletions.
4 changes: 4 additions & 0 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
View file
Expand Up @@ -8709,6 +8709,10 @@ bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
// 3. Other forms of the same operation (intrinsics and other variants)
bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
switch (Inst.getOpcode()) {
case X86::ADD8rr:
case X86::ADD16rr:
case X86::ADD32rr:
case X86::ADD64rr:
case X86::AND8rr:
case X86::AND16rr:
case X86::AND32rr:
Expand Down
184 changes: 92 additions & 92 deletions llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
View file
Expand Up @@ -37,190 +37,190 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: addq %rax, %rax
; CHECK-NEXT: addq %r10, %rax
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: addq %r11, %r8
; CHECK-NEXT: addq %r10, %rax
; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%rdi,%rsi), %r11
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: addq %rdx, %r11
; CHECK-NEXT: leaq (%rdi,%rsi), %rdx
; CHECK-NEXT: addq %r8, %rdx
; CHECK-NEXT: addq %r8, %r11
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: addq %rdx, %r11
; CHECK-NEXT: leaq (%r10,%rcx), %rdx
; CHECK-NEXT: addq %rdx, %rdx
; CHECK-NEXT: addq %rax, %rdx
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rbx, %r9
; CHECK-NEXT: addq %r11, %r9
; CHECK-NEXT: addq %rax, %rdx
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: addq %r11, %rdx
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: leaq (%r8,%rdi), %rbx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rsi, %r11
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: leaq (%r8,%rdi), %rsi
; CHECK-NEXT: addq %r9, %rsi
; CHECK-NEXT: addq %r9, %r11
; CHECK-NEXT: addq %rsi, %r11
; CHECK-NEXT: leaq (%rax,%r10), %rsi
; CHECK-NEXT: addq %rsi, %rsi
; CHECK-NEXT: addq %rdx, %rsi
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %r9, %r11
; CHECK-NEXT: addq %r11, %rcx
; CHECK-NEXT: addq %rdx, %rsi
; CHECK-NEXT: addq %r11, %rsi
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r9,%r8), %r11
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: leaq (%r9,%r8), %rdi
; CHECK-NEXT: addq %rcx, %rdi
; CHECK-NEXT: addq %rcx, %r11
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: leaq (%rdx,%rax), %rdi
; CHECK-NEXT: addq %rdi, %rdi
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %r11, %r10
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: leaq (%rcx,%r9), %rbx
; CHECK-NEXT: addq %r10, %rbx
; CHECK-NEXT: addq %r8, %r11
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: leaq (%rcx,%r9), %r8
; CHECK-NEXT: addq %r10, %r8
; CHECK-NEXT: addq %r10, %r11
; CHECK-NEXT: addq %r8, %r11
; CHECK-NEXT: leaq (%rsi,%rdx), %r8
; CHECK-NEXT: addq %r8, %r8
; CHECK-NEXT: addq %rdi, %r8
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %r10, %r11
; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: addq %rdi, %r8
; CHECK-NEXT: addq %r11, %r8
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r10,%rcx), %r11
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: addq %r9, %r11
; CHECK-NEXT: leaq (%r10,%rcx), %r9
; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: addq %rax, %r11
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: addq %r9, %r11
; CHECK-NEXT: leaq (%rdi,%rsi), %r9
; CHECK-NEXT: addq %r9, %r9
; CHECK-NEXT: addq %r8, %r9
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: addq %r11, %rdx
; CHECK-NEXT: addq %r8, %r9
; CHECK-NEXT: addq %rbx, %r9
; CHECK-NEXT: addq %r11, %r9
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: leaq (%rax,%r10), %rbx
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %rcx, %r11
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: leaq (%rax,%r10), %rcx
; CHECK-NEXT: addq %rdx, %rcx
; CHECK-NEXT: addq %rdx, %r11
; CHECK-NEXT: addq %rcx, %r11
; CHECK-NEXT: leaq (%r8,%rdi), %rcx
; CHECK-NEXT: addq %rcx, %rcx
; CHECK-NEXT: addq %r9, %rcx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %rdx, %r11
; CHECK-NEXT: addq %r11, %rsi
; CHECK-NEXT: addq %r9, %rcx
; CHECK-NEXT: addq %r11, %rcx
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%rdx,%rax), %r11
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: addq %r10, %r11
; CHECK-NEXT: leaq (%rdx,%rax), %r10
; CHECK-NEXT: addq %rsi, %r10
; CHECK-NEXT: addq %rsi, %r11
; CHECK-NEXT: addq %r10, %rbx
; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: addq %r10, %r11
; CHECK-NEXT: leaq (%r9,%r8), %r10
; CHECK-NEXT: addq %r10, %r10
; CHECK-NEXT: addq %rcx, %r10
; CHECK-NEXT: movq X(%rip), %r14
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: addq %rcx, %r10
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: bswapq %r14
; CHECK-NEXT: leaq (%rsi,%rdx), %r11
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: addq %rax, %r14
; CHECK-NEXT: addq %r11, %r14
; CHECK-NEXT: addq %r11, %r10
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%rsi,%rdx), %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%rcx,%r9), %r11
; CHECK-NEXT: addq %r11, %r11
; CHECK-NEXT: addq %r10, %r11
; CHECK-NEXT: movq X(%rip), %rax
; CHECK-NEXT: addq %rdi, %r14
; CHECK-NEXT: addq %r14, %r8
; CHECK-NEXT: addq %rbx, %r8
; CHECK-NEXT: addq %r10, %r11
; CHECK-NEXT: addq %r14, %r11
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: movq X(%rip), %rax
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: leaq (%rdi,%rsi), %rbx
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%rdi,%rsi), %rdx
; CHECK-NEXT: addq %r8, %rdx
; CHECK-NEXT: addq %r8, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: leaq (%r10,%rcx), %rdx
; CHECK-NEXT: addq %rdx, %rdx
; CHECK-NEXT: addq %r11, %rdx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %r8, %rax
; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: addq %r11, %rdx
; CHECK-NEXT: addq %rax, %rdx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: leaq (%r8,%rdi), %rax
; CHECK-NEXT: addq %r9, %rax
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%r11,%r10), %rax
; CHECK-NEXT: addq %rax, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: movq X(%rip), %r14
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rbx, %rcx
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: bswapq %r14
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: leaq (%r9,%r8), %rsi
; CHECK-NEXT: addq %rcx, %rsi
; CHECK-NEXT: addq %rdi, %r14
; CHECK-NEXT: addq %rsi, %r14
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: leaq (%rdx,%r11), %rsi
; CHECK-NEXT: addq %rsi, %rsi
; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: movq X(%rip), %rdi
; CHECK-NEXT: addq %rcx, %r14
; CHECK-NEXT: addq %r14, %r10
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: addq %r14, %rsi
; CHECK-NEXT: bswapq %rdi
; CHECK-NEXT: leaq (%rcx,%r9), %rbx
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: leaq (%rcx,%r9), %rdi
; CHECK-NEXT: addq %r10, %rdi
; CHECK-NEXT: addq %r10, %rbx
; CHECK-NEXT: addq %r8, %rdi
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: leaq (%rax,%rdx), %rdi
; CHECK-NEXT: addq %rdi, %rdi
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: leaq (%rax,%rdx), %r8
; CHECK-NEXT: addq %r8, %r8
; CHECK-NEXT: addq %rsi, %r8
; CHECK-NEXT: addq %r10, %rdi
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: addq %rsi, %r8
; CHECK-NEXT: addq %rdi, %r8
; CHECK-NEXT: movq X(%rip), %rdi
; CHECK-NEXT: bswapq %rdi
; CHECK-NEXT: addq %r9, %rdi
; CHECK-NEXT: movq X(%rip), %r8
; CHECK-NEXT: bswapq %r8
; CHECK-NEXT: addq %r9, %r8
; CHECK-NEXT: leaq (%r10,%rcx), %r9
; CHECK-NEXT: addq %r11, %r9
; CHECK-NEXT: addq %r9, %rdi
; CHECK-NEXT: addq %r11, %r8
; CHECK-NEXT: addq %r9, %r8
; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: addq %rsi, %rsi
; CHECK-NEXT: addq %r8, %rsi
; CHECK-NEXT: addq %r8, %rsi
; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: addq %rdi, %rdx
; CHECK-NEXT: addq %rdi, %rsi
; CHECK-NEXT: addq %rdi, %rsi
; CHECK-NEXT: addq %r8, %rdx
; CHECK-NEXT: addq %r8, %rsi
; CHECK-NEXT: movq X(%rip), %rax
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: addq %r10, %r11
; CHECK-NEXT: movq %rax, X(%rip)
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: addq %rdx, %r11
; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
View file
Expand Up @@ -28,8 +28,8 @@ define cc 11 i32 @caller(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload
; CHECK-NEXT: movl %ebp, %esi
; CHECK-NEXT: calll callee@PLT
; CHECK-NEXT: addl %eax, %ebx
; CHECK-NEXT: addl %ebp, %ebx
; CHECK-NEXT: addl %eax, %ebx
; CHECK-NEXT: movl %ebx, %esi
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/add-sub-bool.ll
View file
Expand Up @@ -68,11 +68,11 @@ define i32 @test_i32_add_add_idx0(i32 %x, i32 %y, i32 %z) nounwind {
;
; X64-LABEL: test_i32_add_add_idx0:
; X64: # %bb.0:
; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: # kill: def $edx killed $edx def $rdx
; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: leal (%rdi,%rsi), %eax
; X64-NEXT: andl $1, %edx
; X64-NEXT: addl %edx, %eax
; X64-NEXT: leal (%rdx,%rdi), %eax
; X64-NEXT: addl %esi, %eax
; X64-NEXT: retq
%add = add i32 %y, %x
%mask = and i32 %z, 1
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/alias-static-alloca.ll
View file
Expand Up @@ -7,15 +7,15 @@
define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movl %esi, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl %edi, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: leal (%rdi,%rsi), %eax
; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: leal (%rsi,%rdx), %eax
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: addl %edi, %eax
; CHECK-NEXT: retq
entry:
%a0 = alloca i32
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/X86/avx512-intrinsics-x86_64.ll
View file
Expand Up @@ -117,10 +117,10 @@ declare i64 @llvm.x86.avx512.cvttss2usi64(<4 x float>, i32) nounwind readnone
define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_avx512_cvtsd2usi64:
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvtsd2usi %xmm0, %rax
; CHECK-NEXT: vcvtsd2usi {rz-sae}, %xmm0, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: vcvtsd2usi %xmm0, %rcx
; CHECK-NEXT: vcvtsd2usi {rz-sae}, %xmm0, %rdx
; CHECK-NEXT: vcvtsd2usi {rd-sae}, %xmm0, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: retq

Expand All @@ -136,10 +136,10 @@ declare i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double>, i32) nounwind readnone
define i64 @test_x86_avx512_cvtsd2si64(<2 x double> %a0) {
; CHECK-LABEL: test_x86_avx512_cvtsd2si64:
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvtsd2si %xmm0, %rax
; CHECK-NEXT: vcvtsd2si {rz-sae}, %xmm0, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: vcvtsd2si %xmm0, %rcx
; CHECK-NEXT: vcvtsd2si {rz-sae}, %xmm0, %rdx
; CHECK-NEXT: vcvtsd2si {rd-sae}, %xmm0, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: retq

Expand All @@ -155,10 +155,10 @@ declare i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double>, i32) nounwind readnone
define i64 @test_x86_avx512_cvtss2usi64(<4 x float> %a0) {
; CHECK-LABEL: test_x86_avx512_cvtss2usi64:
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvtss2usi %xmm0, %rax
; CHECK-NEXT: vcvtss2usi {rz-sae}, %xmm0, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: vcvtss2usi %xmm0, %rcx
; CHECK-NEXT: vcvtss2usi {rz-sae}, %xmm0, %rdx
; CHECK-NEXT: vcvtss2usi {rd-sae}, %xmm0, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: retq

Expand All @@ -174,10 +174,10 @@ declare i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float>, i32) nounwind readnone
define i64 @test_x86_avx512_cvtss2si64(<4 x float> %a0) {
; CHECK-LABEL: test_x86_avx512_cvtss2si64:
; CHECK: ## %bb.0:
; CHECK-NEXT: vcvtss2si %xmm0, %rax
; CHECK-NEXT: vcvtss2si {rz-sae}, %xmm0, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: vcvtss2si %xmm0, %rcx
; CHECK-NEXT: vcvtss2si {rz-sae}, %xmm0, %rdx
; CHECK-NEXT: vcvtss2si {rd-sae}, %xmm0, %rax
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: retq

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