MachO use generic code to detect atomic support.

The default code can detect what width of atomic instructions are supported
based on the targeted architecture profile, version etc so there's no need to
hard-code 64 on Darwin targets (especially as it's wrong in most M-class
cases).

clang/lib/Basic/Targets/ARM.cpp

@@ -1406,11 +1406,6 @@ DarwinARMTargetInfo::DarwinARMTargetInfo(const llvm::Triple &Triple,
                                          const TargetOptions &Opts)
     : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
   HasAlignMac68kSupport = true;
-  // iOS always has 64-bit atomic instructions.
-  // FIXME: This should be based off of the target features in
-  // ARMleTargetInfo.
-  MaxAtomicInlineWidth = 64;
-
   if (Triple.isWatchABI()) {
     // Darwin on iOS uses a variant of the ARM C++ ABI.
     TheCXXABI.set(TargetCXXABI::WatchOS);

clang/test/CodeGen/atomic-arm.c

@@ -0,0 +1,57 @@
+// RUN: %clang_cc1 -triple thumbv6m-apple-unknown-macho %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
+// RUN: %clang_cc1 -triple thumbv7m-apple-unknown-macho %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V7M
+// RUN: %clang_cc1 -triple thumbv7-apple-ios13.0 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HOSTED
+// RUN: %clang_cc1 -triple thumbv7k-apple-watchos5.0 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HOSTED
+
+
+// CHECK-V6M: @always1 = global i32 0
+// CHECK-V6M: @always4 = global i32 0
+// CHECK-V6M: @always8 = global i32 0
+
+// CHECK-V7M: @always1 = global i32 1
+// CHECK-V7M: @always4 = global i32 1
+// CHECK-V7M: @always8 = global i32 0
+
+// CHECK-HOSTED: @always1 = global i32 1
+// CHECK-HOSTED: @always4 = global i32 1
+// CHECK-HOSTED: @always8 = global i32 1
+
+int always1 = __atomic_always_lock_free(1, 0);
+int always4 = __atomic_always_lock_free(4, 0);
+int always8 = __atomic_always_lock_free(8, 0);
+
+int lock_free_1() {
+  // CHECK-LABEL: @lock_free_1
+  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 1, ptr noundef null)
+  // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
+  // CHECK-V6M:   ret i32 [[RES32]]
+
+  // CHECK-V7M: ret i32 1
+  // CHECK-HOSTED: ret i32 1
+  return __c11_atomic_is_lock_free(1);
+}
+
+int lock_free_4() {
+  // CHECK-LABEL: @lock_free_4
+  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 4, ptr noundef null)
+  // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
+  // CHECK-V6M:   ret i32 [[RES32]]
+
+  // CHECK-V7M: ret i32 1
+  // CHECK-HOSTED: ret i32 1
+  return __c11_atomic_is_lock_free(4);
+}
+
+int lock_free_8() {
+  // CHECK-LABEL: @lock_free_8
+  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
+  // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
+  // CHECK-V6M:   ret i32 [[RES32]]
+
+  // CHECK-V7M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
+  // CHECK-V7M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
+  // CHECK-V7M:   ret i32 [[RES32]]
+
+  // CHECK-HOSTED: ret i32 1
+  return __c11_atomic_is_lock_free(8);
+}