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[llvm-exegesis][NFC] Remove extra llvm:: qualifications.
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Summary: First patch: in unit tests.

Subscribers: nemanjai, tschuett, MaskRay, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68687

llvm-svn: 374157
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@legrosbuffle
legrosbuffle committed Oct 9, 2019
1 parent 60db8b7 commit d422d3a
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Showing 13 changed files with 250 additions and 281 deletions.
10 changes: 5 additions & 5 deletions llvm/unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp
View file
Expand Up @@ -34,10 +34,10 @@ constexpr const char kTriple[] = "aarch64-unknown-linux";
class AArch64TargetTest : public ::testing::Test {
protected:
AArch64TargetTest()
: ExegesisTarget_(ExegesisTarget::lookup(llvm::Triple(kTriple))) {
: ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) {
EXPECT_THAT(ExegesisTarget_, NotNull());
std::string error;
Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error);
Target_ = TargetRegistry::lookupTarget(kTriple, error);
EXPECT_THAT(Target_, NotNull());
STI_.reset(
Target_->createMCSubtargetInfo(kTriple, "generic", /*no features*/ ""));
Expand All @@ -54,14 +54,14 @@ class AArch64TargetTest : public ::testing::Test {
return ExegesisTarget_->setRegTo(*STI_, Reg, Value);
}

const llvm::Target *Target_;
const Target *Target_;
const ExegesisTarget *const ExegesisTarget_;
std::unique_ptr<llvm::MCSubtargetInfo> STI_;
std::unique_ptr<MCSubtargetInfo> STI_;
};

TEST_F(AArch64TargetTest, SetRegToConstant) {
// The AArch64 target currently doesn't know how to set register values.
const auto Insts = setRegTo(llvm::AArch64::X0, llvm::APInt());
const auto Insts = setRegTo(AArch64::X0, APInt());
EXPECT_THAT(Insts, Not(IsEmpty()));
}

Expand Down
16 changes: 7 additions & 9 deletions llvm/unittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp
View file
Expand Up @@ -13,8 +13,6 @@ namespace llvm {
namespace exegesis {
namespace {

using llvm::MCInstBuilder;

class ARMMachineFunctionGeneratorTest
: public MachineFunctionGeneratorBaseTest {
protected:
Expand All @@ -30,16 +28,16 @@ class ARMMachineFunctionGeneratorTest
};

TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunction) {
Check({}, llvm::MCInst(), 0x1e, 0xff, 0x2f, 0xe1);
Check({}, MCInst(), 0x1e, 0xff, 0x2f, 0xe1);
}

TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunctionADDrr) {
Check({{llvm::ARM::R0, llvm::APInt()}},
MCInstBuilder(llvm::ARM::ADDrr)
.addReg(llvm::ARM::R0)
.addReg(llvm::ARM::R0)
.addReg(llvm::ARM::R0)
.addImm(llvm::ARMCC::AL)
Check({{ARM::R0, APInt()}},
MCInstBuilder(ARM::ADDrr)
.addReg(ARM::R0)
.addReg(ARM::R0)
.addReg(ARM::R0)
.addImm(ARMCC::AL)
.addReg(0)
.addReg(0),
0x00, 0x00, 0x80, 0xe0, 0x1e, 0xff, 0x2f, 0xe1);
Expand Down
32 changes: 15 additions & 17 deletions llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h
View file
Expand Up @@ -31,14 +31,13 @@ class MachineFunctionGeneratorBaseTest : public ::testing::Test {
MachineFunctionGeneratorBaseTest(const std::string &TT,
const std::string &CpuName)
: TT(TT), CpuName(CpuName),
CanExecute(llvm::Triple(TT).getArch() ==
llvm::Triple(llvm::sys::getProcessTriple()).getArch()),
ET(ExegesisTarget::lookup(llvm::Triple(TT))) {
CanExecute(Triple(TT).getArch() ==
Triple(sys::getProcessTriple()).getArch()),
ET(ExegesisTarget::lookup(Triple(TT))) {
assert(ET);
if (!CanExecute) {
llvm::outs() << "Skipping execution, host:"
<< llvm::sys::getProcessTriple() << ", target:" << TT
<< "\n";
outs() << "Skipping execution, host:" << sys::getProcessTriple()
<< ", target:" << TT << "\n";
}
}

Expand All @@ -61,24 +60,23 @@ class MachineFunctionGeneratorBaseTest : public ::testing::Test {
}

private:
std::unique_ptr<llvm::LLVMTargetMachine> createTargetMachine() {
std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
std::string Error;
const llvm::Target *TheTarget =
llvm::TargetRegistry::lookupTarget(TT, Error);
const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
EXPECT_TRUE(TheTarget) << Error << " " << TT;
const llvm::TargetOptions Options;
llvm::TargetMachine *TM = TheTarget->createTargetMachine(
TT, CpuName, "", Options, llvm::Reloc::Model::Static);
const TargetOptions Options;
TargetMachine *TM = TheTarget->createTargetMachine(TT, CpuName, "", Options,
Reloc::Model::Static);
EXPECT_TRUE(TM) << TT << " " << CpuName;
return std::unique_ptr<llvm::LLVMTargetMachine>(
static_cast<llvm::LLVMTargetMachine *>(TM));
return std::unique_ptr<LLVMTargetMachine>(
static_cast<LLVMTargetMachine *>(TM));
}

ExecutableFunction
assembleToFunction(llvm::ArrayRef<RegisterValue> RegisterInitialValues,
assembleToFunction(ArrayRef<RegisterValue> RegisterInitialValues,
FillFunction Fill) {
llvm::SmallString<256> Buffer;
llvm::raw_svector_ostream AsmStream(Buffer);
SmallString<256> Buffer;
raw_svector_ostream AsmStream(Buffer);
assembleToStream(*ET, createTargetMachine(), /*LiveIns=*/{},
RegisterInitialValues, Fill, AsmStream);
return ExecutableFunction(createTargetMachine(),
Expand Down
15 changes: 8 additions & 7 deletions llvm/unittests/tools/llvm-exegesis/PerfHelperTest.cpp
View file
Expand Up @@ -27,13 +27,14 @@ TEST(PerfHelperTest, FunctionalTest) {
std::string CallbackEventName;
std::string CallbackEventNameFullyQualifed;
int64_t CallbackEventCycles;
Measure(llvm::makeArrayRef(SingleEvent),
[&](const PerfEvent &Event, int64_t Value) {
CallbackEventName = Event.name();
CallbackEventNameFullyQualifed = Event.getPfmEventString();
CallbackEventCycles = Value;
},
EmptyFn);
Measure(
makeArrayRef(SingleEvent),
[&](const PerfEvent &Event, int64_t Value) {
CallbackEventName = Event.name();
CallbackEventNameFullyQualifed = Event.getPfmEventString();
CallbackEventCycles = Value;
},
EmptyFn);
EXPECT_EQ(CallbackEventName, "CYCLES:u");
EXPECT_THAT(CallbackEventNameFullyQualifed, Not(IsEmpty()));
pfmTerminate();
Expand Down
7 changes: 3 additions & 4 deletions llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp
View file
Expand Up @@ -28,10 +28,9 @@ class AnalysisTest : public ::testing::Test {
AnalysisTest() {
const std::string TT = "powerpc64le-unknown-linux";
std::string error;
const llvm::Target *const TheTarget =
llvm::TargetRegistry::lookupTarget(TT, error);
const Target *const TheTarget = TargetRegistry::lookupTarget(TT, error);
if (!TheTarget) {
llvm::errs() << error << "\n";
errs() << error << "\n";
return;
}
STI.reset(TheTarget->createMCSubtargetInfo(TT, "pwr9", ""));
Expand Down Expand Up @@ -63,7 +62,7 @@ class AnalysisTest : public ::testing::Test {
}

protected:
std::unique_ptr<const llvm::MCSubtargetInfo> STI;
std::unique_ptr<const MCSubtargetInfo> STI;
uint16_t ALUIdx = 0;
uint16_t ALUEIdx = 0;
uint16_t ALUOIdx = 0;
Expand Down
11 changes: 5 additions & 6 deletions llvm/unittests/tools/llvm-exegesis/PowerPC/TargetTest.cpp
View file
Expand Up @@ -33,10 +33,10 @@ constexpr const char kTriple[] = "powerpc64le-unknown-linux";
class PowerPCTargetTest : public ::testing::Test {
protected:
PowerPCTargetTest()
: ExegesisTarget_(ExegesisTarget::lookup(llvm::Triple(kTriple))) {
: ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) {
EXPECT_THAT(ExegesisTarget_, NotNull());
std::string error;
Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error);
Target_ = TargetRegistry::lookupTarget(kTriple, error);
EXPECT_THAT(Target_, NotNull());
}
static void SetUpTestCase() {
Expand All @@ -46,15 +46,14 @@ class PowerPCTargetTest : public ::testing::Test {
InitializePowerPCExegesisTarget();
}

const llvm::Target *Target_;
const Target *Target_;
const ExegesisTarget *const ExegesisTarget_;
};

TEST_F(PowerPCTargetTest, SetRegToConstant) {
const std::unique_ptr<llvm::MCSubtargetInfo> STI(
const std::unique_ptr<MCSubtargetInfo> STI(
Target_->createMCSubtargetInfo(kTriple, "generic", ""));
const auto Insts =
ExegesisTarget_->setRegTo(*STI, llvm::PPC::X0, llvm::APInt());
const auto Insts = ExegesisTarget_->setRegTo(*STI, PPC::X0, APInt());
EXPECT_THAT(Insts, Not(IsEmpty()));
}

Expand Down
8 changes: 4 additions & 4 deletions llvm/unittests/tools/llvm-exegesis/RegisterValueTest.cpp
View file
Expand Up @@ -16,12 +16,12 @@ namespace exegesis {
namespace {

#define CHECK(EXPECTED, ACTUAL) \
EXPECT_EQ(llvm::APInt(SizeInBits, EXPECTED, 16), \
EXPECT_EQ(APInt(SizeInBits, EXPECTED, 16), \
bitcastFloatValue(Semantic, PredefinedValues::ACTUAL))

TEST(RegisterValueTest, Half) {
const size_t SizeInBits = 16;
const auto &Semantic = llvm::APFloatBase::IEEEhalf();
const auto &Semantic = APFloatBase::IEEEhalf();
CHECK("0000", POS_ZERO);
CHECK("8000", NEG_ZERO);
CHECK("3C00", ONE);
Expand All @@ -37,7 +37,7 @@ TEST(RegisterValueTest, Half) {

TEST(RegisterValueTest, Single) {
const size_t SizeInBits = 32;
const auto &Semantic = llvm::APFloatBase::IEEEsingle();
const auto &Semantic = APFloatBase::IEEEsingle();
CHECK("00000000", POS_ZERO);
CHECK("80000000", NEG_ZERO);
CHECK("3F800000", ONE);
Expand All @@ -53,7 +53,7 @@ TEST(RegisterValueTest, Single) {

TEST(RegisterValueTest, Double) {
const size_t SizeInBits = 64;
const auto &Semantic = llvm::APFloatBase::IEEEdouble();
const auto &Semantic = APFloatBase::IEEEdouble();
CHECK("0000000000000000", POS_ZERO);
CHECK("8000000000000000", NEG_ZERO);
CHECK("3FF0000000000000", ONE);
Expand Down
4 changes: 2 additions & 2 deletions llvm/unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp
View file
Expand Up @@ -38,11 +38,11 @@ class X86MachineFunctionGeneratorTest
};

TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunction) {
Check({}, llvm::MCInst(), 0xc3);
Check({}, MCInst(), 0xc3);
}

TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunctionXOR32rr_X86) {
Check({{EAX, llvm::APInt(32, 1)}},
Check({{EAX, APInt(32, 1)}},
MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX),
// mov eax, 1
0xb8, 0x01, 0x00, 0x00, 0x00,
Expand Down
24 changes: 12 additions & 12 deletions llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp
View file
Expand Up @@ -32,9 +32,9 @@ bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) {
std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue);
}

static std::string Dump(const llvm::MCInst &McInst) {
static std::string Dump(const MCInst &McInst) {
std::string Buffer;
llvm::raw_string_ostream OS(Buffer);
raw_string_ostream OS(Buffer);
McInst.print(OS);
return Buffer;
}
Expand All @@ -59,19 +59,19 @@ TEST(BenchmarkResultTest, WriteToAndReadFromDisk) {
// Read benchmarks.
const LLVMState State("x86_64-unknown-linux", "haswell");

llvm::ExitOnError ExitOnErr;
ExitOnError ExitOnErr;

InstructionBenchmark ToDisk;

ToDisk.Key.Instructions.push_back(llvm::MCInstBuilder(llvm::X86::XOR32rr)
.addReg(llvm::X86::AL)
.addReg(llvm::X86::AH)
ToDisk.Key.Instructions.push_back(MCInstBuilder(X86::XOR32rr)
.addReg(X86::AL)
.addReg(X86::AH)
.addImm(123)
.addFPImm(0.5));
ToDisk.Key.Config = "config";
ToDisk.Key.RegisterInitialValues = {
RegisterValue{llvm::X86::AL, llvm::APInt(8, "-1", 10)},
RegisterValue{llvm::X86::AH, llvm::APInt(8, "123", 10)}};
RegisterValue{X86::AL, APInt(8, "-1", 10)},
RegisterValue{X86::AH, APInt(8, "123", 10)}};
ToDisk.Mode = InstructionBenchmark::Latency;
ToDisk.CpuName = "cpu_name";
ToDisk.LLVMTriple = "llvm_triple";
Expand All @@ -81,12 +81,12 @@ TEST(BenchmarkResultTest, WriteToAndReadFromDisk) {
ToDisk.Error = "error";
ToDisk.Info = "info";

llvm::SmallString<64> Filename;
SmallString<64> Filename;
std::error_code EC;
EC = llvm::sys::fs::createUniqueDirectory("BenchmarkResultTestDir", Filename);
EC = sys::fs::createUniqueDirectory("BenchmarkResultTestDir", Filename);
ASSERT_FALSE(EC);
llvm::sys::path::append(Filename, "data.yaml");
llvm::errs() << Filename << "-------\n";
sys::path::append(Filename, "data.yaml");
errs() << Filename << "-------\n";
ExitOnErr(ToDisk.writeYaml(State, Filename));

{
Expand Down
39 changes: 18 additions & 21 deletions llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp
View file
Expand Up @@ -27,48 +27,45 @@ class RegisterAliasingTest : public X86TestBase {};

TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
const auto &RegInfo = State.getRegInfo();
const RegisterAliasingTracker tracker(RegInfo, llvm::X86::EAX);
std::set<llvm::MCPhysReg> ActualAliasedRegisters;
const RegisterAliasingTracker tracker(RegInfo, X86::EAX);
std::set<MCPhysReg> ActualAliasedRegisters;
for (unsigned I : tracker.aliasedBits().set_bits())
ActualAliasedRegisters.insert(static_cast<llvm::MCPhysReg>(I));
const std::set<llvm::MCPhysReg> ExpectedAliasedRegisters = {
llvm::X86::AL, llvm::X86::AH, llvm::X86::AX,
llvm::X86::EAX, llvm::X86::HAX, llvm::X86::RAX};
ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
const std::set<MCPhysReg> ExpectedAliasedRegisters = {
X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
for (llvm::MCPhysReg aliased : ExpectedAliasedRegisters) {
ASSERT_THAT(tracker.getOrigin(aliased), llvm::X86::EAX);
for (MCPhysReg aliased : ExpectedAliasedRegisters) {
ASSERT_THAT(tracker.getOrigin(aliased), X86::EAX);
}
}

TEST_F(RegisterAliasingTest, TrackRegisterClass) {
// The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for
// AL, BL, CL and DL.
const auto &RegInfo = State.getRegInfo();
const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
const BitVector NoReservedReg(RegInfo.getNumRegs());

const RegisterAliasingTracker RegClassTracker(
RegInfo, NoReservedReg,
RegInfo.getRegClass(llvm::X86::GR8_ABCD_LRegClassID));
RegInfo, NoReservedReg, RegInfo.getRegClass(X86::GR8_ABCD_LRegClassID));

llvm::BitVector sum(RegInfo.getNumRegs());
sum |= RegisterAliasingTracker(RegInfo, llvm::X86::AL).aliasedBits();
sum |= RegisterAliasingTracker(RegInfo, llvm::X86::BL).aliasedBits();
sum |= RegisterAliasingTracker(RegInfo, llvm::X86::CL).aliasedBits();
sum |= RegisterAliasingTracker(RegInfo, llvm::X86::DL).aliasedBits();
BitVector sum(RegInfo.getNumRegs());
sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits();
sum |= RegisterAliasingTracker(RegInfo, X86::BL).aliasedBits();
sum |= RegisterAliasingTracker(RegInfo, X86::CL).aliasedBits();
sum |= RegisterAliasingTracker(RegInfo, X86::DL).aliasedBits();

ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
}

TEST_F(RegisterAliasingTest, TrackRegisterClassCache) {
// Fetching twice the same tracker yields the same pointers.
const auto &RegInfo = State.getRegInfo();
const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
const BitVector NoReservedReg(RegInfo.getNumRegs());
RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
ASSERT_THAT(&Cache.getRegister(llvm::X86::AX),
&Cache.getRegister(llvm::X86::AX));
ASSERT_THAT(&Cache.getRegister(X86::AX), &Cache.getRegister(X86::AX));

ASSERT_THAT(&Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID),
&Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID));
ASSERT_THAT(&Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID),
&Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID));
}

} // namespace
Expand Down
2 changes: 1 addition & 1 deletion llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp
View file
Expand Up @@ -54,7 +54,7 @@ class SchedClassResolutionTest : public X86TestBase {
}

protected:
const llvm::MCSubtargetInfo &STI;
const MCSubtargetInfo &STI;
uint16_t P0Idx = 0;
uint16_t P1Idx = 0;
uint16_t P5Idx = 0;
Expand Down

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