[VE] Fix vmp0 subregister mapping

vmp0 is the all-ones v512i1 register and does not break down into
subregisters.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D120054

llvm/lib/Target/VE/VERegisterInfo.td

@@ -152,8 +152,10 @@ foreach I = 0-15 in
   def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>;
 
 // Aliases of VMs to use as a pair of two VM for packed instructions
+def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]>;
+
 let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in
-foreach I = 0-7 in
+foreach I = 1-7 in
   def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I,
                         [!cast<VEMaskReg>("VM"#!shl(I,1)),
                          !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))],

llvm/test/CodeGen/VE/VELIntrinsics/extract.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
 
 ;;; Test extract intrinsic instructions
@@ -22,7 +23,6 @@ declare <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1>)
 define fastcc <256 x i1> @extract_vm512l(<512 x i1> %0) {
 ; CHECK-LABEL: extract_vm512l:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andm %vm0, %vm0, %vm2
 ; CHECK-NEXT:    andm %vm1, %vm0, %vm3
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1> %0)