Skip to content

Commit

Permalink
[RISCV] Add mayRaiseFPException to RISCV scalar FP instructions.
Browse files Browse the repository at this point in the history 
FRM dependency will be added in a future patch.

Reviewed By: arcbbb

Differential Revision: https://reviews.llvm.org/D115540
  • Loading branch information
@topperc
topperc committed Dec 14, 2021
1 parent b79686c commit d4d7640
Show file tree
Hide file tree
Showing 3 changed files with 21 additions and 9 deletions.
6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoD.td
View file
Expand Up @@ -76,7 +76,8 @@ def FSQRT_D : FPUnaryOp_r_frm<0b0101101, 0b00000, FPR64, FPR64, "fsqrt.d">,
Sched<[WriteFSqrt64, ReadFSqrt64]>;
def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;

let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64] in {
let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64],
mayRaiseFPException = 0 in {
def FSGNJ_D : FPALU_rr<0b0010001, 0b000, "fsgnj.d", FPR64>;
def FSGNJN_D : FPALU_rr<0b0010001, 0b001, "fsgnjn.d", FPR64>;
def FSGNJX_D : FPALU_rr<0b0010001, 0b010, "fsgnjx.d", FPR64>;
Expand All @@ -100,6 +101,7 @@ def FLT_D : FPCmp_rr<0b1010001, 0b001, "flt.d", FPR64>;
def FLE_D : FPCmp_rr<0b1010001, 0b000, "fle.d", FPR64>;
}

let mayRaiseFPException = 0 in
def FCLASS_D : FPUnaryOp_r<0b1110001, 0b00000, 0b001, GPR, FPR64, "fclass.d">,
Sched<[WriteFClass64, ReadFClass64]>;

Expand Down Expand Up @@ -127,6 +129,7 @@ def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, 0b00011, GPR, FPR64, "fcvt.lu.d">,
Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
def : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>;

let mayRaiseFPException = 0 in
def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;

Expand All @@ -138,6 +141,7 @@ def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, 0b00011, FPR64, GPR, "fcvt.d.lu">,
Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
def : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>;

let mayRaiseFPException = 0 in
def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">,
Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;
} // Predicates = [HasStdExtD, IsRV64]
Expand Down
18 changes: 11 additions & 7 deletions llvm/lib/Target/RISCV/RISCVInstrInfoF.td
View file
Expand Up @@ -59,7 +59,7 @@ def frmarg : Operand<XLenVT> {
// Instruction class templates
//===----------------------------------------------------------------------===//

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPFMA_rrr_frm<RISCVOpcode opcode, bits<2> funct2, string opcodestr,
RegisterClass rty>
: RVInstR4Frm<funct2, opcode, (outs rty:$rd),
Expand All @@ -71,13 +71,13 @@ class FPFMADynFrmAlias<FPFMA_rrr_frm Inst, string OpcodeStr,
: InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
(Inst rty:$rd, rty:$rs1, rty:$rs2, rty:$rs3, 0b111)>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
RegisterClass rty>
: RVInstR<funct7, funct3, OPC_OP_FP, (outs rty:$rd),
(ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2">;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPALU_rr_frm<bits<7> funct7, string opcodestr, RegisterClass rty>
: RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
(ins rty:$rs1, rty:$rs2, frmarg:$funct3), opcodestr,
Expand All @@ -88,15 +88,15 @@ class FPALUDynFrmAlias<FPALU_rr_frm Inst, string OpcodeStr,
: InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
(Inst rty:$rd, rty:$rs1, rty:$rs2, 0b111)>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPUnaryOp_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
RegisterClass rdty, RegisterClass rs1ty, string opcodestr>
: RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
opcodestr, "$rd, $rs1"> {
let rs2 = rs2val;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPUnaryOp_r_frm<bits<7> funct7, bits<5> rs2val, RegisterClass rdty,
RegisterClass rs1ty, string opcodestr>
: RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
Expand All @@ -110,7 +110,7 @@ class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
: InstAlias<OpcodeStr#" $rd, $rs1",
(Inst rdty:$rd, rs1ty:$rs1, 0b111)>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPCmp_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
RegisterClass rty>
: RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
Expand Down Expand Up @@ -166,7 +166,8 @@ def FSQRT_S : FPUnaryOp_r_frm<0b0101100, 0b00000, FPR32, FPR32, "fsqrt.s">,
Sched<[WriteFSqrt32, ReadFSqrt32]>;
def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>;

let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32] in {
let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32],
mayRaiseFPException = 0 in {
def FSGNJ_S : FPALU_rr<0b0010000, 0b000, "fsgnj.s", FPR32>;
def FSGNJN_S : FPALU_rr<0b0010000, 0b001, "fsgnjn.s", FPR32>;
def FSGNJX_S : FPALU_rr<0b0010000, 0b010, "fsgnjx.s", FPR32>;
Expand All @@ -185,6 +186,7 @@ def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, 0b00001, GPR, FPR32, "fcvt.wu.s">,
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;

let mayRaiseFPException = 0 in
def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;

Expand All @@ -194,6 +196,7 @@ def FLT_S : FPCmp_rr<0b1010000, 0b001, "flt.s", FPR32>;
def FLE_S : FPCmp_rr<0b1010000, 0b000, "fle.s", FPR32>;
}

let mayRaiseFPException = 0 in
def FCLASS_S : FPUnaryOp_r<0b1110000, 0b00000, 0b001, GPR, FPR32, "fclass.s">,
Sched<[WriteFClass32, ReadFClass32]>;

Expand All @@ -205,6 +208,7 @@ def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, 0b00001, FPR32, GPR, "fcvt.s.wu">,
Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>;

let mayRaiseFPException = 0 in
def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
} // Predicates = [HasStdExtF]
Expand Down
6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
View file
Expand Up @@ -79,7 +79,8 @@ def FSQRT_H : FPUnaryOp_r_frm<0b0101110, 0b00000, FPR16, FPR16, "fsqrt.h">,
Sched<[WriteFSqrt16, ReadFSqrt16]>;
def : FPUnaryOpDynFrmAlias<FSQRT_H, "fsqrt.h", FPR16, FPR16>;

let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16] in {
let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16],
mayRaiseFPException = 0 in {
def FSGNJ_H : FPALU_rr<0b0010010, 0b000, "fsgnj.h", FPR16>;
def FSGNJN_H : FPALU_rr<0b0010010, 0b001, "fsgnjn.h", FPR16>;
def FSGNJX_H : FPALU_rr<0b0010010, 0b010, "fsgnjx.h", FPR16>;
Expand Down Expand Up @@ -115,9 +116,11 @@ def : FPUnaryOpDynFrmAlias<FCVT_H_S, "fcvt.h.s", FPR16, FPR32>;
def FCVT_S_H : FPUnaryOp_r<0b0100000, 0b00010, 0b000, FPR32, FPR16, "fcvt.s.h">,
Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;

let mayRaiseFPException = 0 in
def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">,
Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>;

let mayRaiseFPException = 0 in
def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">,
Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>;
} // Predicates = [HasStdExtZfhmin]
Expand All @@ -130,6 +133,7 @@ def FLT_H : FPCmp_rr<0b1010010, 0b001, "flt.h", FPR16>;
def FLE_H : FPCmp_rr<0b1010010, 0b000, "fle.h", FPR16>;
}

let mayRaiseFPException = 0 in
def FCLASS_H : FPUnaryOp_r<0b1110010, 0b00000, 0b001, GPR, FPR16, "fclass.h">,
Sched<[WriteFClass16, ReadFClass16]>;
} // Predicates = [HasStdExtZfh]
Expand Down

0 comments on commit d4d7640

Please sign in to comment.