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[PowerPC] Eliminate integer compare instructions - vol. 5
Adds handling for i64 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33720 llvm-svn: 304907
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ | ||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ | ||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl | ||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ | ||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ | ||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl | ||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
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@glob = common local_unnamed_addr global i64 0, align 8 | ||
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define signext i32 @test_inesll(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_inesll: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: addic r4, r3, -1 | ||
; CHECK-NEXT: subfe r3, r4, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%conv = zext i1 %cmp to i32 | ||
ret i32 %conv | ||
} | ||
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define signext i32 @test_inesll_sext(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_inesll_sext: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%sub = sext i1 %cmp to i32 | ||
ret i32 %sub | ||
} | ||
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define signext i32 @test_inesll_z(i64 %a) { | ||
; CHECK-LABEL: test_inesll_z: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addic r4, r3, -1 | ||
; CHECK-NEXT: subfe r3, r4, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%conv = zext i1 %cmp to i32 | ||
ret i32 %conv | ||
} | ||
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define signext i32 @test_inesll_sext_z(i64 %a) { | ||
; CHECK-LABEL: test_inesll_sext_z: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%sub = sext i1 %cmp to i32 | ||
ret i32 %sub | ||
} | ||
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define void @test_inesll_store(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_inesll_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5) | ||
; CHECK-NEXT: addic r5, r3, -1 | ||
; CHECK-NEXT: subfe r3, r5, r3 | ||
; CHECK-NEXT: std r3, 0(r12) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%conv1 = zext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} | ||
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define void @test_inesll_sext_store(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_inesll_sext_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5) | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: std r3, 0(r12) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%conv1 = sext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} | ||
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define void @test_inesll_z_store(i64 %a) { | ||
; CHECK-LABEL: test_inesll_z_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha | ||
; CHECK-NEXT: addic r5, r3, -1 | ||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) | ||
; CHECK-NEXT: subfe r3, r5, r3 | ||
; CHECK-NEXT: std r3, 0(r4) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%conv1 = zext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} | ||
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define void @test_inesll_sext_z_store(i64 %a) { | ||
; CHECK-LABEL: test_inesll_sext_z_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: std r3, 0(r4) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%conv1 = sext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,125 @@ | ||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ | ||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ | ||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl | ||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ | ||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ | ||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl | ||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
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@glob = common local_unnamed_addr global i64 0, align 8 | ||
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define signext i32 @test_ineull(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_ineull: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: addic r4, r3, -1 | ||
; CHECK-NEXT: subfe r3, r4, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%conv = zext i1 %cmp to i32 | ||
ret i32 %conv | ||
} | ||
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define signext i32 @test_ineull_sext(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_ineull_sext: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%sub = sext i1 %cmp to i32 | ||
ret i32 %sub | ||
} | ||
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define signext i32 @test_ineull_z(i64 %a) { | ||
; CHECK-LABEL: test_ineull_z: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addic r4, r3, -1 | ||
; CHECK-NEXT: subfe r3, r4, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%conv = zext i1 %cmp to i32 | ||
ret i32 %conv | ||
} | ||
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define signext i32 @test_ineull_sext_z(i64 %a) { | ||
; CHECK-LABEL: test_ineull_sext_z: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%sub = sext i1 %cmp to i32 | ||
ret i32 %sub | ||
} | ||
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define void @test_ineull_store(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_ineull_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5) | ||
; CHECK-NEXT: addic r5, r3, -1 | ||
; CHECK-NEXT: subfe r3, r5, r3 | ||
; CHECK-NEXT: std r3, 0(r12) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%conv1 = zext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} | ||
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define void @test_ineull_sext_store(i64 %a, i64 %b) { | ||
; CHECK-LABEL: test_ineull_sext_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha | ||
; CHECK-NEXT: xor r3, r3, r4 | ||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5) | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: std r3, 0(r12) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, %b | ||
%conv1 = sext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} | ||
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define void @test_ineull_z_store(i64 %a) { | ||
; CHECK-LABEL: test_ineull_z_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha | ||
; CHECK-NEXT: addic r5, r3, -1 | ||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) | ||
; CHECK-NEXT: subfe r3, r5, r3 | ||
; CHECK-NEXT: std r3, 0(r4) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%conv1 = zext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} | ||
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define void @test_ineull_sext_z_store(i64 %a) { | ||
; CHECK-LABEL: test_ineull_sext_z_store: | ||
; CHECK: # BB#0: # %entry | ||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha | ||
; CHECK-NEXT: subfic r3, r3, 0 | ||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) | ||
; CHECK-NEXT: subfe r3, r3, r3 | ||
; CHECK-NEXT: std r3, 0(r4) | ||
; CHECK-NEXT: blr | ||
entry: | ||
%cmp = icmp ne i64 %a, 0 | ||
%conv1 = sext i1 %cmp to i64 | ||
store i64 %conv1, i64* @glob, align 8 | ||
ret void | ||
} |
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