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[flang] Add PowerPC vec_stxvp and vsx_stxvp intrinsic
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Differential Revision: https://reviews.llvm.org/D157768
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@kkwli
kkwli committed Aug 14, 2023
1 parent 17f331c commit d9c2c6f
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Showing 5 changed files with 399 additions and 2 deletions.
1 change: 1 addition & 0 deletions flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ enum class VecOp {
St,
Ste,
Stxv,
Stxvp,
Sub,
Xor,
Xst,
Expand Down
19 changes: 18 additions & 1 deletion flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -223,6 +223,11 @@ static constexpr IntrinsicHandler ppcHandlers[]{
&PI::genVecXStore<VecOp::Stxv>),
{{{"arg1", asValue}, {"arg2", asValue}, {"arg3", asAddr}}},
/*isElemental=*/false},
{"__ppc_vec_stxvp",
static_cast<IntrinsicLibrary::SubroutineGenerator>(
&PI::genVecStore<VecOp::Stxvp>),
{{{"arg1", asValue}, {"arg2", asValue}, {"arg3", asAddr}}},
/*isElemental=*/false},
{"__ppc_vec_sub",
static_cast<IntrinsicLibrary::ExtendedGenerator>(
&PI::genVecAddAndMulSubXor<VecOp::Sub>),
Expand Down Expand Up @@ -1788,6 +1793,11 @@ void PPCIntrinsicLibrary::genVecStore(llvm::ArrayRef<fir::ExtendedValue> args) {
assert(false && "unknown type");
break;
}
case VecOp::Stxvp:
// __vector_pair type
stTy = mlir::VectorType::get(256, mlir::IntegerType::get(context, 1));
fname = "llvm.ppc.vsx.stxvp";
break;
default:
llvm_unreachable("invalid vector operation for generator");
}
Expand All @@ -1798,11 +1808,18 @@ void PPCIntrinsicLibrary::genVecStore(llvm::ArrayRef<fir::ExtendedValue> args) {

llvm::SmallVector<mlir::Value, 4> biArgs;

mlir::Value newArg1;
if (vop == VecOp::Stxvp) {
biArgs.push_back(argBases[0]);
biArgs.push_back(addr);
builder.create<fir::CallOp>(loc, funcOp, biArgs);
return;
}

auto vecTyInfo{getVecTypeFromFirType(argBases[0].getType())};
auto cnv{builder.createConvert(loc, vecTyInfo.toMlirVectorType(context),
argBases[0])};

mlir::Value newArg1{nullptr};
if (stTy != arg1TyInfo.toMlirVectorType(context))
newArg1 = builder.create<mlir::vector::BitCastOp>(loc, stTy, cnv);
else
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112 changes: 112 additions & 0 deletions flang/module/__ppc_intrinsics.f90
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Original file line number Diff line number Diff line change
Expand Up @@ -384,13 +384,76 @@ pure subroutine sub_vr##VKIND##ir##VKIND(arg1, arg2, arg3); \
!dir$ ignore_tkr(r) arg3; \
end subroutine ;

! subroutine(__vector_pair, i, __vector_pair)
pure subroutine sub_vpi0vp(arg1, arg2, arg3)
__vector_pair, intent(in) :: arg1
integer(8), intent(in) :: arg2
!dir$ ignore_tkr(k) arg2
__vector_pair, intent(out) :: arg3
!dir$ ignore_tkr(r) arg3
end subroutine

! subroutine(__vector_pair, i, vector(i))
#define SUB_VPI0VI(VKIND) \
pure subroutine sub_vpi0vi##VKIND(arg1, arg2, arg3); \
__vector_pair, intent(in) :: arg1; \
integer(8), intent(in) :: arg2; \
!dir$ ignore_tkr(k) arg2; \
vector(integer(VKIND)), intent(out) :: arg3; \
!dir$ ignore_tkr(r) arg3; \
end subroutine;

! subroutine(__vector_pair, i, vector(u))
#define SUB_VPI0VU(VKIND) \
pure subroutine sub_vpi0vu##VKIND(arg1, arg2, arg3); \
__vector_pair, intent(in) :: arg1; \
integer(8), intent(in) :: arg2; \
!dir$ ignore_tkr(k) arg2; \
vector(unsigned(VKIND)), intent(out) :: arg3; \
!dir$ ignore_tkr(r) arg3; \
end subroutine;

! subroutine(__vector_pair, i, vector(r))
#define SUB_VPI0VR(VKIND) \
pure subroutine sub_vpi0vr##VKIND(arg1, arg2, arg3); \
__vector_pair, intent(in) :: arg1; \
integer(8), intent(in) :: arg2; \
!dir$ ignore_tkr(k) arg2; \
vector(real(VKIND)), intent(out) :: arg3; \
!dir$ ignore_tkr(r) arg3; \
end subroutine;

! subroutine(__vector_pair, i, i)
pure subroutine sub_vpi0i0(arg1, arg2, arg3)
__vector_pair, intent(in) :: arg1
integer(8), intent(in) :: arg2
!dir$ ignore_tkr(k) arg2
integer(8), intent(out) :: arg3
!dir$ ignore_tkr(kr) arg3
end subroutine

! subroutine(__vector_pair, i, r)
pure subroutine sub_vpi0r0(arg1, arg2, arg3)
__vector_pair, intent(in) :: arg1
integer(8), intent(in) :: arg2
!dir$ ignore_tkr(k) arg2
real(8), intent(out) :: arg3
!dir$ ignore_tkr(kr) arg3
end subroutine

SUB_VIIVI(1) SUB_VIIVI(2) SUB_VIIVI(4) SUB_VIIVI(8)
SUB_VUIVU(1) SUB_VUIVU(2) SUB_VUIVU(4) SUB_VUIVU(8)
SUB_VRIVR(4) SUB_VRIVR(8)
SUB_VIII(1) SUB_VIII(2) SUB_VIII(4) SUB_VIII(8)
SUB_VUII(1) SUB_VUII(2) SUB_VUII(4) SUB_VUII(8)
SUB_VRIR(4) SUB_VRIR(8)
SUB_VPI0VI(1) SUB_VPI0VI(2) SUB_VPI0VI(4) SUB_VPI0VI(8)
SUB_VPI0VU(1) SUB_VPI0VU(2) SUB_VPI0VU(4) SUB_VPI0VU(8)
SUB_VPI0VR(4) SUB_VPI0VR(8)

#undef SUB_VPI0VR
#undef SUB_VPI0VU
#undef SUB_VPI0VI
#undef SUB_VRIR
#undef SUB_VUII
#undef SUB_VIII
Expand Down Expand Up @@ -1328,4 +1391,53 @@ end function func_r8r8i
#undef SUB_VU_I_I
#undef SUB_VR_Ik_R

!-----------------------------------------------------------------------
! subroutine(__vector_pair, integer, __vector_pair/vector/integer/real)
!-----------------------------------------------------------------------
#define VP_I0_VI(NAME, VKIND) __ppc_##NAME##_vpi0vi##VKIND
#define VP_I0_VU(NAME, VKIND) __ppc_##NAME##_vpi0vu##VKIND
#define VP_I0_VR(NAME, VKIND) __ppc_##NAME##_vpi0vr##VKIND

#define VEC_VP_I0_VI(NAME, VKIND) \
procedure(sub_vpi0vi##VKIND) :: VP_I0_VI(NAME, VKIND);
#define VEC_VP_I0_VU(NAME, VKIND) \
procedure(sub_vpi0vu##VKIND) :: VP_I0_VU(NAME, VKIND);
#define VEC_VP_I0_VR(NAME, VKIND) \
procedure(sub_vpi0vr##VKIND) :: VP_I0_VR(NAME, VKIND);

! vec_stxvp
procedure(sub_vpi0vp) :: __ppc_vec_stxvp_vpi0vp0
procedure(sub_vpi0i0) :: __ppc_vec_stxvp_vpi0i0
procedure(sub_vpi0r0) :: __ppc_vec_stxvp_vpi0r0
VEC_VP_I0_VI(vec_stxvp, 1) VEC_VP_I0_VI(vec_stxvp, 2) VEC_VP_I0_VI(vec_stxvp, 4) VEC_VP_I0_VI(vec_stxvp, 8)
VEC_VP_I0_VU(vec_stxvp, 1) VEC_VP_I0_VU(vec_stxvp, 2) VEC_VP_I0_VU(vec_stxvp, 4) VEC_VP_I0_VU(vec_stxvp, 8)
VEC_VP_I0_VR(vec_stxvp, 4) VEC_VP_I0_VR(vec_stxvp, 8)
interface vec_stxvp
procedure :: __ppc_vec_stxvp_vpi0vp0
procedure :: __ppc_vec_stxvp_vpi0i0
procedure :: __ppc_vec_stxvp_vpi0r0
procedure :: VP_I0_VI(vec_stxvp, 1), VP_I0_VI(vec_stxvp, 2), VP_I0_VI(vec_stxvp, 4), VP_I0_VI(vec_stxvp, 8)
procedure :: VP_I0_VU(vec_stxvp, 1), VP_I0_VU(vec_stxvp, 2), VP_I0_VU(vec_stxvp, 4), VP_I0_VU(vec_stxvp, 8)
procedure :: VP_I0_VR(vec_stxvp, 4), VP_I0_VR(vec_stxvp, 8)
end interface vec_stxvp
public :: vec_stxvp

! vsx_stxvp (alias to vec_stxvp)
interface vsx_stxvp
procedure :: __ppc_vec_stxvp_vpi0vp0
procedure :: __ppc_vec_stxvp_vpi0i0
procedure :: __ppc_vec_stxvp_vpi0r0
procedure :: VP_I0_VI(vec_stxvp, 1), VP_I0_VI(vec_stxvp, 2), VP_I0_VI(vec_stxvp, 4), VP_I0_VI(vec_stxvp, 8)
procedure :: VP_I0_VU(vec_stxvp, 1), VP_I0_VU(vec_stxvp, 2), VP_I0_VU(vec_stxvp, 4), VP_I0_VU(vec_stxvp, 8)
procedure :: VP_I0_VR(vec_stxvp, 4), VP_I0_VR(vec_stxvp, 8)
end interface vsx_stxvp
public :: vsx_stxvp

#undef VEC_VP_I0_VR
#undef VEC_VP_I0_VU
#undef VEC_VP_I0_VI
#undef VP_I0_VR
#undef VP_I0_VU
#undef VP_I0_VI

end module __ppc_intrinsics

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