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[AMDGPU][NFC] Refactor some uses of unsigned to Register
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Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76035
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@slinder1
slinder1 committed Mar 19, 2020
1 parent 30bb113 commit db099f9
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Showing 3 changed files with 52 additions and 52 deletions.
7 changes: 5 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View file
Expand Up @@ -1051,11 +1051,14 @@ bool GCNTargetMachine::parseMachineFunctionInfo(

MFI->initializeBaseYamlFields(YamlMFI);

auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) {
if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) {
auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
// FIXME: Update parseNamedRegsiterReference to take a Register.
unsigned TempReg;
if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
SourceRange = RegName.SourceRange;
return true;
}
RegVal = TempReg;

return false;
};
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18 changes: 9 additions & 9 deletions llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
View file
Expand Up @@ -212,7 +212,7 @@ void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
MF.getFunction()));
}

unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
const SIRegisterInfo &TRI) {
ArgInfo.PrivateSegmentBuffer =
ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
Expand All @@ -221,43 +221,43 @@ unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
return ArgInfo.PrivateSegmentBuffer.getRegister();
}

unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
NumUserSGPRs += 2;
return ArgInfo.DispatchPtr.getRegister();
}

unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
NumUserSGPRs += 2;
return ArgInfo.QueuePtr.getRegister();
}

unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
ArgInfo.KernargSegmentPtr
= ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
NumUserSGPRs += 2;
return ArgInfo.KernargSegmentPtr.getRegister();
}

unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
NumUserSGPRs += 2;
return ArgInfo.DispatchID.getRegister();
}

unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
NumUserSGPRs += 2;
return ArgInfo.FlatScratchInit.getRegister();
}

unsigned SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
NumUserSGPRs += 2;
Expand Down Expand Up @@ -310,7 +310,7 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
// Make sure to handle the case where a wide SGPR spill may span between two
// VGPRs.
for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
unsigned LaneVGPR;
Register LaneVGPR;
unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);

if (VGPRIndex == 0) {
Expand Down Expand Up @@ -442,7 +442,7 @@ MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
}

static yaml::StringValue regToString(unsigned Reg,
static yaml::StringValue regToString(Register Reg,
const TargetRegisterInfo &TRI) {
yaml::StringValue Dest;
{
Expand Down
79 changes: 38 additions & 41 deletions llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
View file
Expand Up @@ -331,20 +331,20 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
friend class GCNTargetMachine;

unsigned TIDReg = AMDGPU::NoRegister;
Register TIDReg = AMDGPU::NoRegister;

// Registers that may be reserved for spilling purposes. These may be the same
// as the input registers.
unsigned ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
unsigned ScratchWaveOffsetReg = AMDGPU::SCRATCH_WAVE_OFFSET_REG;
Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
Register ScratchWaveOffsetReg = AMDGPU::SCRATCH_WAVE_OFFSET_REG;

// This is the current function's incremented size from the kernel's scratch
// wave offset register. For an entry function, this is exactly the same as
// the ScratchWaveOffsetReg.
unsigned FrameOffsetReg = AMDGPU::FP_REG;
Register FrameOffsetReg = AMDGPU::FP_REG;

// Top of the stack SGPR offset derived from the ScratchWaveOffsetReg.
unsigned StackPtrOffsetReg = AMDGPU::SP_REG;
Register StackPtrOffsetReg = AMDGPU::SP_REG;

AMDGPUFunctionArgInfo ArgInfo;

Expand Down Expand Up @@ -437,25 +437,25 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {

public:
struct SpilledReg {
unsigned VGPR = 0;
Register VGPR;
int Lane = -1;

SpilledReg() = default;
SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}

bool hasLane() { return Lane != -1;}
bool hasReg() { return VGPR != 0;}
};

struct SGPRSpillVGPRCSR {
// VGPR used for SGPR spills
unsigned VGPR;
Register VGPR;

// If the VGPR is a CSR, the stack slot used to save/restore it in the
// prolog/epilog.
Optional<int> FI;

SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {}
SGPRSpillVGPRCSR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
};

struct VGPRSpillToAGPR {
Expand All @@ -465,12 +465,9 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {

SparseBitVector<> WWMReservedRegs;

void ReserveWWMRegister(unsigned reg) { WWMReservedRegs.set(reg); }
void ReserveWWMRegister(Register Reg) { WWMReservedRegs.set(Reg); }

private:
// SGPR->VGPR spilling support.
using SpillRegMask = std::pair<unsigned, unsigned>;

// Track VGPR + wave index for each subregister of the SGPR spilled to
// frameindex key.
DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
Expand All @@ -488,7 +485,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
public: // FIXME
/// If this is set, an SGPR used for save/restore of the register used for the
/// frame pointer.
unsigned SGPRForFPSaveRestoreCopy = 0;
Register SGPRForFPSaveRestoreCopy;
Optional<int> FramePointerSaveIndex;

public:
Expand Down Expand Up @@ -527,8 +524,8 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
void removeDeadFrameIndices(MachineFrameInfo &MFI);

bool hasCalculatedTID() const { return TIDReg != 0; };
unsigned getTIDReg() const { return TIDReg; };
void setTIDReg(unsigned Reg) { TIDReg = Reg; }
Register getTIDReg() const { return TIDReg; };
void setTIDReg(Register Reg) { TIDReg = Reg; }

unsigned getBytesInStackArgArea() const {
return BytesInStackArgArea;
Expand All @@ -539,34 +536,34 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
}

// Add user SGPRs.
unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
unsigned addDispatchPtr(const SIRegisterInfo &TRI);
unsigned addQueuePtr(const SIRegisterInfo &TRI);
unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
unsigned addDispatchID(const SIRegisterInfo &TRI);
unsigned addFlatScratchInit(const SIRegisterInfo &TRI);
unsigned addImplicitBufferPtr(const SIRegisterInfo &TRI);
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
Register addDispatchPtr(const SIRegisterInfo &TRI);
Register addQueuePtr(const SIRegisterInfo &TRI);
Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
Register addDispatchID(const SIRegisterInfo &TRI);
Register addFlatScratchInit(const SIRegisterInfo &TRI);
Register addImplicitBufferPtr(const SIRegisterInfo &TRI);

// Add system SGPRs.
unsigned addWorkGroupIDX() {
Register addWorkGroupIDX() {
ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
NumSystemSGPRs += 1;
return ArgInfo.WorkGroupIDX.getRegister();
}

unsigned addWorkGroupIDY() {
Register addWorkGroupIDY() {
ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
NumSystemSGPRs += 1;
return ArgInfo.WorkGroupIDY.getRegister();
}

unsigned addWorkGroupIDZ() {
Register addWorkGroupIDZ() {
ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
NumSystemSGPRs += 1;
return ArgInfo.WorkGroupIDZ.getRegister();
}

unsigned addWorkGroupInfo() {
Register addWorkGroupInfo() {
ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
NumSystemSGPRs += 1;
return ArgInfo.WorkGroupInfo.getRegister();
Expand All @@ -585,14 +582,14 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
ArgInfo.WorkItemIDZ = Arg;
}

unsigned addPrivateSegmentWaveByteOffset() {
Register addPrivateSegmentWaveByteOffset() {
ArgInfo.PrivateSegmentWaveByteOffset
= ArgDescriptor::createRegister(getNextSystemSGPR());
NumSystemSGPRs += 1;
return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
}

void setPrivateSegmentWaveByteOffset(unsigned Reg) {
void setPrivateSegmentWaveByteOffset(Register Reg) {
ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
}

Expand Down Expand Up @@ -698,35 +695,35 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
return NumUserSGPRs + NumSystemSGPRs;
}

unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const {
Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
}

/// Returns the physical register reserved for use as the resource
/// descriptor for scratch accesses.
unsigned getScratchRSrcReg() const {
Register getScratchRSrcReg() const {
return ScratchRSrcReg;
}

void setScratchRSrcReg(unsigned Reg) {
void setScratchRSrcReg(Register Reg) {
assert(Reg != 0 && "Should never be unset");
ScratchRSrcReg = Reg;
}

unsigned getScratchWaveOffsetReg() const {
Register getScratchWaveOffsetReg() const {
return ScratchWaveOffsetReg;
}

unsigned getFrameOffsetReg() const {
Register getFrameOffsetReg() const {
return FrameOffsetReg;
}

void setFrameOffsetReg(unsigned Reg) {
void setFrameOffsetReg(Register Reg) {
assert(Reg != 0 && "Should never be unset");
FrameOffsetReg = Reg;
}

void setStackPtrOffsetReg(unsigned Reg) {
void setStackPtrOffsetReg(Register Reg) {
assert(Reg != 0 && "Should never be unset");
StackPtrOffsetReg = Reg;
}
Expand All @@ -735,20 +732,20 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
// NoRegister. This is mostly a workaround for MIR tests where state that
// can't be directly computed from the function is not preserved in serialized
// MIR.
unsigned getStackPtrOffsetReg() const {
Register getStackPtrOffsetReg() const {
return StackPtrOffsetReg;
}

void setScratchWaveOffsetReg(unsigned Reg) {
void setScratchWaveOffsetReg(Register Reg) {
assert(Reg != 0 && "Should never be unset");
ScratchWaveOffsetReg = Reg;
}

unsigned getQueuePtrUserSGPR() const {
Register getQueuePtrUserSGPR() const {
return ArgInfo.QueuePtr.getRegister();
}

unsigned getImplicitBufferPtrUserSGPR() const {
Register getImplicitBufferPtrUserSGPR() const {
return ArgInfo.ImplicitBufferPtr.getRegister();
}

Expand Down Expand Up @@ -861,7 +858,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
}

/// \returns SGPR used for \p Dim's work group ID.
unsigned getWorkGroupIDSGPR(unsigned Dim) const {
Register getWorkGroupIDSGPR(unsigned Dim) const {
switch (Dim) {
case 0:
assert(hasWorkGroupIDX());
Expand Down

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