[MachineVerifier] Try harder to verify LiveIntervals

Verify the LiveIntervals analysis after a pass that claims to preserve it, even if there are no further passes (apart from the verifier itself) that would use the analysis. Fixes #46217 Differential Revision: https://reviews.llvm.org/D129208
llvm · May 24, 2023 · db54627 · db54627
1 parent 78bf8a0
commit db54627
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Showing 6 changed files with 6 additions and 34 deletions.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -297,6 +297,7 @@ namespace {
       AU.addUsedIfAvailable<LiveStacks>();
       AU.addUsedIfAvailable<LiveVariables>();
       AU.addUsedIfAvailable<SlotIndexes>();
+      AU.addUsedIfAvailable<LiveIntervals>();
       AU.setPreservesAll();
       MachineFunctionPass::getAnalysisUsage(AU);
     }

diff --git a/llvm/test/CodeGen/AArch64/regcoal-physreg.mir b/llvm/test/CodeGen/AArch64/regcoal-physreg.mir
@@ -1,8 +1,4 @@
-# RUN: llc -mtriple=aarch64-apple-ios -run-pass=simple-register-coalescing,simple-register-coalescing -verify-machineinstrs %s -o - | FileCheck %s
-
-# FIXME: Second run of the pass is a workaround for a bug in
-# -run-pass. The verifier doesn't detect broken LiveIntervals, see bug
-# 46873
+# RUN: llc -mtriple=aarch64-apple-ios -run-pass=simple-register-coalescing -verify-machineinstrs %s -o - | FileCheck %s
 --- |
   declare void @f2()
 

diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
@@ -1,9 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra,si-optimize-exec-masking-pre-ra %s -o - | FileCheck --check-prefix=GCN %s
-
-# FIXME: Second run of the pass is a workaround for a bug in
-# -run-pass. The verifier doesn't detect broken LiveIntervals, see bug
-# 46873
+# RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck --check-prefix=GCN %s
 
 # %8 is defined at the end, but it will be used in bb.2.
 # Make sure we properly extend its liverange to the beginning of the bb.2.

diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
@@ -1,9 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra,si-optimize-exec-masking-pre-ra -o - %s | FileCheck %s
-
-# FIXME: Second run of the pass is a workaround for a bug in
-# -run-pass. The verifier doesn't detect broken LiveIntervals, see bug
-# 46873
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck %s
 
 
 # Cannot fold this without moving the def of %7 after the and.

diff --git a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
@@ -1,31 +1,14 @@
 # RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
 # REQUIRES: asserts
 
-# CHECK: INTERVALS
-# CHECK: %0
-# CHECK-LABEL: Machine code for function test0:
-
 # CHECK: INTERVALS
 # CHECK: %0
 # CHECK-LABEL: Machine code for function test1:
 
 --- |
-  define amdgpu_kernel void @test0() { ret void }
   define amdgpu_kernel void @test1() { ret void }
 ...
 ---
-name: test0
-registers:
-  - { id: 0, class: sreg_64 }
-body: |
-  bb.0:
-    S_NOP 0, implicit-def %0
-    S_NOP 0, implicit %0
-
-    S_NOP 0, implicit-def undef %0.sub0
-    S_NOP 0, implicit %0
-...
----
 name: test1
 registers:
   - { id: 0, class: sreg_64 }

diff --git a/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll b/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
@@ -62,8 +62,8 @@ zero:
 ; CHECK:      bb.5
 ; CHECK:        %3:gr64 = COPY %10
 ; CHECK-LV:     %4:gr64 = COPY killed %10
-; CHECK-LV:     %4:gr64 = nuw ADD64ri32 %4, 8, implicit-def dead $eflags
-; CHECK-LIS:    %4:gr64 = LEA64r %10, 1, $noreg, 8, $noreg
+; CHECK-LIS:    %4:gr64 = COPY %10
+; CHECK:        %4:gr64 = nuw ADD64ri32 %4, 8, implicit-def dead $eflags
 ; CHECK:        TEST64rr killed %1, %1, implicit-def $eflags
 ; CHECK:        JCC_1 %bb.1, 5, implicit killed $eflags
 ; CHECK:        JMP_1 %bb.6