FastISel: Partially use Register

Doesn't try to convert the cases that depend on generated code.

llvm/include/llvm/CodeGen/FastISel.h

@@ -88,7 +88,7 @@ class FastISel {
     ArgListTy Args;
     ImmutableCallSite *CS = nullptr;
     MachineInstr *Call = nullptr;
-    unsigned ResultReg = 0;
+    Register ResultReg;
     unsigned NumResultRegs = 0;
 
     SmallVector<Value *, 16> OutVals;
@@ -199,7 +199,7 @@ class FastISel {
   };
 
 protected:
-  DenseMap<const Value *, unsigned> LocalValueMap;
+  DenseMap<const Value *, Register> LocalValueMap;
   FunctionLoweringInfo &FuncInfo;
   MachineFunction *MF;
   MachineRegisterInfo &MRI;
@@ -270,16 +270,16 @@ class FastISel {
 
   /// Create a virtual register and arrange for it to be assigned the
   /// value for the given LLVM value.
-  unsigned getRegForValue(const Value *V);
+  Register getRegForValue(const Value *V);
 
   /// Look up the value to see if its value is already cached in a
   /// register. It may be defined by instructions across blocks or defined
   /// locally.
-  unsigned lookUpRegForValue(const Value *V);
+  Register lookUpRegForValue(const Value *V);
 
   /// This is a wrapper around getRegForValue that also takes care of
   /// truncating or sign-extending the given getelementptr index value.
-  std::pair<unsigned, bool> getRegForGEPIndex(const Value *Idx);
+  std::pair<Register, bool> getRegForGEPIndex(const Value *Idx);
 
   /// We're checking to see if we can fold \p LI into \p FoldInst. Note
   /// that we could have a sequence where multiple LLVM IR instructions are
@@ -374,7 +374,7 @@ class FastISel {
   /// It first tries to emit an instruction with an immediate operand using
   /// fastEmit_ri.  If that fails, it materializes the immediate into a register
   /// and try fastEmit_rr instead.
-  unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
+  Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
                         uint64_t Imm, MVT ImmType);
 
   /// This method is called by target-independent code to request that an
@@ -389,66 +389,66 @@ class FastISel {
 
   /// Emit a MachineInstr with no operands and a result register in the
   /// given register class.
-  unsigned fastEmitInst_(unsigned MachineInstOpcode,
+  Register fastEmitInst_(unsigned MachineInstOpcode,
                          const TargetRegisterClass *RC);
 
   /// Emit a MachineInstr with one register operand and a result register
   /// in the given register class.
-  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
+  Register fastEmitInst_r(unsigned MachineInstOpcode,
                           const TargetRegisterClass *RC, unsigned Op0,
                           bool Op0IsKill);
 
   /// Emit a MachineInstr with two register operands and a result
   /// register in the given register class.
-  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
+  Register fastEmitInst_rr(unsigned MachineInstOpcode,
                            const TargetRegisterClass *RC, unsigned Op0,
                            bool Op0IsKill, unsigned Op1, bool Op1IsKill);
 
   /// Emit a MachineInstr with three register operands and a result
   /// register in the given register class.
-  unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
+  Register fastEmitInst_rrr(unsigned MachineInstOpcode,
                             const TargetRegisterClass *RC, unsigned Op0,
                             bool Op0IsKill, unsigned Op1, bool Op1IsKill,
                             unsigned Op2, bool Op2IsKill);
 
   /// Emit a MachineInstr with a register operand, an immediate, and a
   /// result register in the given register class.
-  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
+  Register fastEmitInst_ri(unsigned MachineInstOpcode,
                            const TargetRegisterClass *RC, unsigned Op0,
                            bool Op0IsKill, uint64_t Imm);
 
   /// Emit a MachineInstr with one register operand and two immediate
   /// operands.
-  unsigned fastEmitInst_rii(unsigned MachineInstOpcode,
+  Register fastEmitInst_rii(unsigned MachineInstOpcode,
                             const TargetRegisterClass *RC, unsigned Op0,
                             bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
 
   /// Emit a MachineInstr with a floating point immediate, and a result
   /// register in the given register class.
-  unsigned fastEmitInst_f(unsigned MachineInstOpcode,
+  Register fastEmitInst_f(unsigned MachineInstOpcode,
                           const TargetRegisterClass *RC,
                           const ConstantFP *FPImm);
 
   /// Emit a MachineInstr with two register operands, an immediate, and a
   /// result register in the given register class.
-  unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
+  Register fastEmitInst_rri(unsigned MachineInstOpcode,
                             const TargetRegisterClass *RC, unsigned Op0,
                             bool Op0IsKill, unsigned Op1, bool Op1IsKill,
                             uint64_t Imm);
 
   /// Emit a MachineInstr with a single immediate operand, and a result
   /// register in the given register class.
-  unsigned fastEmitInst_i(unsigned MachineInstOpcode,
+  Register fastEmitInst_i(unsigned MachineInstOpcode,
                           const TargetRegisterClass *RC, uint64_t Imm);
 
   /// Emit a MachineInstr for an extract_subreg from a specified index of
   /// a superregister to a specified type.
-  unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
+  Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
                                       uint32_t Idx);
 
   /// Emit MachineInstrs to compute the value of Op with all but the
   /// least significant bit set to zero.
-  unsigned fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
+  Register fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
 
   /// Emit an unconditional branch to the given block, unless it is the
   /// immediate (fall-through) successor, and update the CFG.
@@ -466,14 +466,14 @@ class FastISel {
   /// NOTE: This is only necessary because we might select a block that uses a
   /// value before we select the block that defines the value. It might be
   /// possible to fix this by selecting blocks in reverse postorder.
-  void updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1);
+  void updateValueMap(const Value *I, Register Reg, unsigned NumRegs = 1);
 
-  unsigned createResultReg(const TargetRegisterClass *RC);
+  Register createResultReg(const TargetRegisterClass *RC);
 
   /// Try to constrain Op so that it is usable by argument OpNum of the
   /// provided MCInstrDesc. If this fails, create a new virtual register in the
   /// correct class and COPY the value there.
-  unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
+  Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
                                     unsigned OpNum);
 
   /// Emit a constant in a register using target-specific logic, such as
@@ -558,12 +558,12 @@ class FastISel {
 
   /// Helper for materializeRegForValue to materialize a constant in a
   /// target-independent way.
-  unsigned materializeConstant(const Value *V, MVT VT);
+  Register materializeConstant(const Value *V, MVT VT);
 
   /// Helper for getRegForVale. This function is called when the value
   /// isn't already available in a register and must be materialized with new
   /// instructions.
-  unsigned materializeRegForValue(const Value *V, MVT VT);
+  Register materializeRegForValue(const Value *V, MVT VT);
 
   /// Clears LocalValueMap and moves the area for the new local variables
   /// to the beginning of the block. It helps to avoid spilling cached variables
@@ -584,7 +584,7 @@ class FastISel {
 
   /// Sinks the local value materialization instruction LocalMI to its first use
   /// in the basic block, or deletes it if it is not used.
-  void sinkLocalValueMaterialization(MachineInstr &LocalMI, unsigned DefReg,
+  void sinkLocalValueMaterialization(MachineInstr &LocalMI, Register DefReg,
                                      InstOrderMap &OrderMap);
 
   /// Insertion point before trying to select the current instruction.