[llvm-mca] Rename Backend to Pipeline. NFC.

Summary:
This change renames the Backend and BackendPrinter to Pipeline and PipelinePrinter respectively. 
Variables and comments have also been updated to reflect this change.

The reason for this rename, is to be slightly more correct about what MCA is modeling.  MCA models a Pipeline, which implies some logical sequence of stages. 

Reviewers: andreadb, courbet, RKSimon

Reviewed By: andreadb, courbet

Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D48496

llvm-svn: 335496

llvm/tools/llvm-mca/CMakeLists.txt

@@ -10,8 +10,6 @@ set(LLVM_LINK_COMPONENTS
   )
 
 add_llvm_tool(llvm-mca
-  Backend.cpp
-  BackendPrinter.cpp
   CodeRegion.cpp
   DispatchStage.cpp
   DispatchStatistics.cpp
@@ -24,6 +22,8 @@ add_llvm_tool(llvm-mca
   InstructionTables.cpp
   LSUnit.cpp
   llvm-mca.cpp
+  Pipeline.cpp
+  PipelinePrinter.cpp
   RegisterFile.cpp
   RegisterFileStatistics.cpp
   ResourcePressureView.cpp

llvm/tools/llvm-mca/DispatchStage.cpp

@@ -17,8 +17,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "DispatchStage.h"
-#include "Backend.h"
 #include "HWEventListener.h"
+#include "Pipeline.h"
 #include "Scheduler.h"
 #include "llvm/Support/Debug.h"
 

llvm/tools/llvm-mca/DispatchStage.h

@@ -30,7 +30,7 @@ namespace mca {
 
 class WriteState;
 class Scheduler;
-class Backend;
+class Pipeline;
 
 // Implements the hardware dispatch logic.
 //
@@ -54,7 +54,7 @@ class DispatchStage : public Stage {
   unsigned DispatchWidth;
   unsigned AvailableEntries;
   unsigned CarryOver;
-  Backend *Owner;
+  Pipeline *Owner;
   const llvm::MCSubtargetInfo &STI;
   RetireControlUnit &RCU;
   RegisterFile &PRF;
@@ -84,12 +84,12 @@ class DispatchStage : public Stage {
   }
 
 public:
-  DispatchStage(Backend *B, const llvm::MCSubtargetInfo &Subtarget,
+  DispatchStage(Pipeline *P, const llvm::MCSubtargetInfo &Subtarget,
                 const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
                 unsigned MaxDispatchWidth, RetireControlUnit &R,
                 RegisterFile &F, Scheduler &Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
-        CarryOver(0U), Owner(B), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
+        CarryOver(0U), Owner(P), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
 
   // We can always try to dispatch, so returning false is okay in this case.
   // The retire stage, which controls the RCU, might have items to complete but

llvm/tools/llvm-mca/ExecuteStage.cpp

@@ -16,7 +16,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "ExecuteStage.h"
-#include "Backend.h"
+#include "Pipeline.h"
 #include "Scheduler.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"

llvm/tools/llvm-mca/ExecuteStage.h

@@ -26,11 +26,11 @@
 
 namespace mca {
 
-class Backend;
+class Pipeline;
 
 class ExecuteStage : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
-  Backend *Owner;
+  Pipeline *Owner;
   RetireControlUnit &RCU;
   Scheduler &HWS;
 
@@ -40,8 +40,8 @@ class ExecuteStage : public Stage {
   void issueReadyInstructions();
 
 public:
-  ExecuteStage(Backend *B, RetireControlUnit &R, Scheduler &S)
-      : Stage(), Owner(B), RCU(R), HWS(S) {}
+  ExecuteStage(Pipeline *P, RetireControlUnit &R, Scheduler &S)
+      : Stage(), Owner(P), RCU(R), HWS(S) {}
   ExecuteStage(const ExecuteStage &Other) = delete;
   ExecuteStage &operator=(const ExecuteStage &Other) = delete;
 

llvm/tools/llvm-mca/HWEventListener.h

@@ -27,11 +27,11 @@ namespace mca {
 class HWInstructionEvent {
 public:
   // This is the list of event types that are shared by all targets, that
-  // generic subtarget-agnostic classes (e.g. Backend, HWInstructionEvent, ...)
-  // and generic Views can manipulate.
+  // generic subtarget-agnostic classes (e.g., Pipeline, HWInstructionEvent,
+  // ...) and generic Views can manipulate.
   // Subtargets are free to define additional event types, that are goin to be
   // handled by generic components as opaque values, but can still be
-  // emitted by subtarget-specific pipeline components (e.g. Scheduler,
+  // emitted by subtarget-specific pipeline stages (e.g., ExecuteStage,
   // DispatchStage, ...) and interpreted by subtarget-specific EventListener
   // implementations.
   enum GenericEventType {
@@ -116,7 +116,7 @@ class HWStallEvent {
 
 class HWEventListener {
 public:
-  // Generic events generated by the backend pipeline.
+  // Generic events generated by the pipeline.
   virtual void onCycleBegin() {}
   virtual void onCycleEnd() {}
 

llvm/tools/llvm-mca/Instruction.cpp

@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines abstractions used by the Backend to model register reads,
+// This file defines abstractions used by the Pipeline to model register reads,
 // register writes and instructions.
 //
 //===----------------------------------------------------------------------===//

llvm/tools/llvm-mca/Instruction.h

@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file defines abstractions used by the Backend to model register reads,
+/// This file defines abstractions used by the Pipeline to model register reads,
 /// register writes and instructions.
 ///
 //===----------------------------------------------------------------------===//
@@ -264,10 +264,10 @@ struct InstrDesc {
   bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }
 };
 
-/// An instruction dispatched to the out-of-order backend.
+/// An instruction propagated through the simulated instruction pipeline.
 ///
-/// This class is used to monitor changes in the internal state of instructions
-/// that are dispatched by the DispatchUnit to the hardware schedulers.
+/// This class is used to monitor changes to the internal state of instructions
+/// that are sent to the various components of the simulated hardware pipeline.
 class Instruction {
   const InstrDesc &Desc;
 

llvm/tools/llvm-mca/InstructionTables.cpp

@@ -11,7 +11,7 @@
 /// This file implements method InstructionTables::run().
 /// Method run() prints a theoretical resource pressure distribution based on
 /// the information available in the scheduling model, and without running
-/// the backend pipeline.
+/// the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 

llvm/tools/llvm-mca/Backend.cpp → llvm/tools/llvm-mca/Pipeline.cpp

@@ -1,4 +1,4 @@
-//===--------------------- Backend.cpp --------------------------*- C++ -*-===//
+//===--------------------- Pipeline.cpp -------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -8,11 +8,12 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// Implementation of class Backend which emulates an hardware OoO backend.
+/// This file implements an ordered container of stages that simulate the
+/// pipeline of a hardware backend.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Backend.h"
+#include "Pipeline.h"
 #include "HWEventListener.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/Support/Debug.h"
@@ -23,12 +24,12 @@ namespace mca {
 
 using namespace llvm;
 
-void Backend::addEventListener(HWEventListener *Listener) {
+void Pipeline::addEventListener(HWEventListener *Listener) {
   if (Listener)
     Listeners.insert(Listener);
 }
 
-bool Backend::hasWorkToProcess() {
+bool Pipeline::hasWorkToProcess() {
   const auto It = llvm::find_if(Stages, [](const std::unique_ptr<Stage> &S) {
     return S->hasWorkToComplete();
   });
@@ -37,24 +38,24 @@ bool Backend::hasWorkToProcess() {
 
 // This routine returns early if any stage returns 'false' after execute() is
 // called on it.
-bool Backend::executeStages(InstRef &IR) {
+bool Pipeline::executeStages(InstRef &IR) {
   for (const std::unique_ptr<Stage> &S : Stages)
     if (!S->execute(IR))
       return false;
   return true;
 }
 
-void Backend::postExecuteStages(const InstRef &IR) {
+void Pipeline::postExecuteStages(const InstRef &IR) {
   for (const std::unique_ptr<Stage> &S : Stages)
     S->postExecute(IR);
 }
 
-void Backend::run() {
+void Pipeline::run() {
   while (hasWorkToProcess())
     runCycle(Cycles++);
 }
 
-void Backend::runCycle(unsigned Cycle) {
+void Pipeline::runCycle(unsigned Cycle) {
   notifyCycleBegin(Cycle);
 
   // Update the stages before we do any processing for this cycle.
@@ -70,40 +71,40 @@ void Backend::runCycle(unsigned Cycle) {
   notifyCycleEnd(Cycle);
 }
 
-void Backend::notifyCycleBegin(unsigned Cycle) {
+void Pipeline::notifyCycleBegin(unsigned Cycle) {
   LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleBegin();
 }
 
-void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
+void Pipeline::notifyInstructionEvent(const HWInstructionEvent &Event) {
   for (HWEventListener *Listener : Listeners)
     Listener->onInstructionEvent(Event);
 }
 
-void Backend::notifyStallEvent(const HWStallEvent &Event) {
+void Pipeline::notifyStallEvent(const HWStallEvent &Event) {
   for (HWEventListener *Listener : Listeners)
     Listener->onStallEvent(Event);
 }
 
-void Backend::notifyResourceAvailable(const ResourceRef &RR) {
+void Pipeline::notifyResourceAvailable(const ResourceRef &RR) {
   LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
                     << RR.second << "]\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onResourceAvailable(RR);
 }
 
-void Backend::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {
+void Pipeline::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {
   for (HWEventListener *Listener : Listeners)
     Listener->onReservedBuffers(Buffers);
 }
 
-void Backend::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
+void Pipeline::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
   for (HWEventListener *Listener : Listeners)
     Listener->onReleasedBuffers(Buffers);
 }
 
-void Backend::notifyCycleEnd(unsigned Cycle) {
+void Pipeline::notifyCycleEnd(unsigned Cycle) {
   LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleEnd();

llvm/tools/llvm-mca/Backend.h → llvm/tools/llvm-mca/Pipeline.h

@@ -1,4 +1,4 @@
-//===--------------------- Backend.h ----------------------------*- C++ -*-===//
+//===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -8,12 +8,13 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements an OoO backend for the llvm-mca tool.
+/// This file implements an ordered container of stages that simulate the
+/// pipeline of a hardware backend.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_BACKEND_H
-#define LLVM_TOOLS_LLVM_MCA_BACKEND_H
+#ifndef LLVM_TOOLS_LLVM_MCA_PIPELINE_H
+#define LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 
 #include "Scheduler.h"
 #include "Stage.h"
@@ -25,7 +26,7 @@ class HWEventListener;
 class HWInstructionEvent;
 class HWStallEvent;
 
-/// An out of order backend for a specific subtarget.
+/// A pipeline for a specific subtarget.
 ///
 /// It emulates an out-of-order execution of instructions. Instructions are
 /// fetched from a MCInst sequence managed by an initial 'Fetch' stage.
@@ -42,15 +43,15 @@ class HWStallEvent;
 /// is defined by the SourceMgr object, which is managed by the initial stage
 /// of the instruction pipeline.
 ///
-/// The Backend entry point is method 'run()' which executes cycles in a loop
+/// The Pipeline entry point is method 'run()' which executes cycles in a loop
 /// until there are new instructions to dispatch, and not every instruction
 /// has been retired.
 ///
-/// Internally, the Backend collects statistical information in the form of
+/// Internally, the Pipeline collects statistical information in the form of
 /// histograms. For example, it tracks how the dispatch group size changes
 /// over time.
-class Backend {
-  /// An ordered list of stages that define this backend's instruction pipeline.
+class Pipeline {
+  /// An ordered list of stages that define this instruction pipeline.
   llvm::SmallVector<std::unique_ptr<Stage>, 8> Stages;
   std::set<HWEventListener *> Listeners;
   unsigned Cycles;
@@ -61,9 +62,9 @@ class Backend {
   void runCycle(unsigned Cycle);
 
 public:
-  Backend(unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
-          unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0,
-          bool AssumeNoAlias = false)
+  Pipeline(unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
+           unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0,
+           bool AssumeNoAlias = false)
       : Cycles(0) {}
   void appendStage(std::unique_ptr<Stage> S) { Stages.push_back(std::move(S)); }
   void run();
@@ -78,4 +79,4 @@ class Backend {
 };
 } // namespace mca
 
-#endif
+#endif // LLVM_TOOLS_LLVM_MCA_PIPELINE_H

llvm/tools/llvm-mca/BackendPrinter.cpp → llvm/tools/llvm-mca/PipelinePrinter.cpp

@@ -1,4 +1,4 @@
-//===--------------------- BackendPrinter.cpp -------------------*- C++ -*-===//
+//===--------------------- PipelinePrinter.cpp ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -8,19 +8,19 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements the BackendPrinter interface.
+/// This file implements the PipelinePrinter interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "BackendPrinter.h"
+#include "PipelinePrinter.h"
 #include "View.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 
 namespace mca {
 
 using namespace llvm;
 
-void BackendPrinter::printReport(llvm::raw_ostream &OS) const {
+void PipelinePrinter::printReport(llvm::raw_ostream &OS) const {
   for (const auto &V : Views)
     V->printView(OS);
 }