[DAGCombiner] Improve X div/rem Y fold if single bit element type

Summary: Tests by @spatel, thanks

Reviewers: spatel, RKSimon

Reviewed By: spatel

Subscribers: sdardis, atanasyan, llvm-commits, spatel

Differential Revision: https://reviews.llvm.org/D52668

llvm-svn: 345575

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -3138,11 +3138,12 @@ static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
 
   // X / 1 -> X
   // X % 1 -> 0
-  if (N1C && N1C->isOne())
-    return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
   // If this is a boolean op (single-bit element type), we can't have
   // division-by-zero or remainder-by-zero, so assume the divisor is 1.
-  // Similarly, if we're zero-extending a boolean divisor, then assume it's a 1.
+  // TODO: Similarly, if we're zero-extending a boolean divisor, then assume
+  // it's a 1.
+  if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
+    return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
 
   return SDValue();
 }

llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll

@@ -35,55 +35,32 @@
 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
 ; GP32-LABEL: sdiv_i1:
 ; GP32:       # %bb.0: # %entry
-; GP32-NEXT:    div $zero, $4, $5
-; GP32-NEXT:    teq $5, $zero, 7
-; GP32-NEXT:    mflo $1
-; GP32-NEXT:    andi $1, $1, 1
 ; GP32-NEXT:    jr $ra
-; GP32-NEXT:    negu $2, $1
+; GP32-NEXT:    move $2, $4
 ;
 ; GP32R6-LABEL: sdiv_i1:
 ; GP32R6:       # %bb.0: # %entry
-; GP32R6-NEXT:    div $1, $4, $5
-; GP32R6-NEXT:    teq $5, $zero, 7
-; GP32R6-NEXT:    andi $1, $1, 1
 ; GP32R6-NEXT:    jr $ra
-; GP32R6-NEXT:    negu $2, $1
+; GP32R6-NEXT:    move $2, $4
 ;
 ; GP64-LABEL: sdiv_i1:
 ; GP64:       # %bb.0: # %entry
-; GP64-NEXT:    div $zero, $4, $5
-; GP64-NEXT:    teq $5, $zero, 7
-; GP64-NEXT:    mflo $1
-; GP64-NEXT:    andi $1, $1, 1
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    negu $2, $1
+; GP64-NEXT:    move $2, $4
 ;
 ; GP64R6-LABEL: sdiv_i1:
 ; GP64R6:       # %bb.0: # %entry
-; GP64R6-NEXT:    div $1, $4, $5
-; GP64R6-NEXT:    teq $5, $zero, 7
-; GP64R6-NEXT:    andi $1, $1, 1
 ; GP64R6-NEXT:    jr $ra
-; GP64R6-NEXT:    negu $2, $1
+; GP64R6-NEXT:    move $2, $4
 ;
 ; MMR3-LABEL: sdiv_i1:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    div $zero, $4, $5
-; MMR3-NEXT:    teq $5, $zero, 7
-; MMR3-NEXT:    mflo16 $2
-; MMR3-NEXT:    andi16 $2, $2, 1
-; MMR3-NEXT:    li16 $3, 0
-; MMR3-NEXT:    subu16 $2, $3, $2
+; MMR3-NEXT:    move $2, $4
 ; MMR3-NEXT:    jrc $ra
 ;
 ; MMR6-LABEL: sdiv_i1:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    div $2, $4, $5
-; MMR6-NEXT:    teq $5, $zero, 7
-; MMR6-NEXT:    andi16 $2, $2, 1
-; MMR6-NEXT:    li16 $3, 0
-; MMR6-NEXT:    subu16 $2, $3, $2
+; MMR6-NEXT:    move $2, $4
 ; MMR6-NEXT:    jrc $ra
 entry:
   %r = sdiv i1 %a, %b

llvm/test/CodeGen/Mips/llvm-ir/srem.ll

@@ -35,55 +35,32 @@
 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
 ; GP32-LABEL: srem_i1:
 ; GP32:       # %bb.0: # %entry
-; GP32-NEXT:    div $zero, $4, $5
-; GP32-NEXT:    teq $5, $zero, 7
-; GP32-NEXT:    mfhi $1
-; GP32-NEXT:    andi $1, $1, 1
 ; GP32-NEXT:    jr $ra
-; GP32-NEXT:    negu $2, $1
+; GP32-NEXT:    addiu $2, $zero, 0
 ;
 ; GP32R6-LABEL: srem_i1:
 ; GP32R6:       # %bb.0: # %entry
-; GP32R6-NEXT:    mod $1, $4, $5
-; GP32R6-NEXT:    teq $5, $zero, 7
-; GP32R6-NEXT:    andi $1, $1, 1
 ; GP32R6-NEXT:    jr $ra
-; GP32R6-NEXT:    negu $2, $1
+; GP32R6-NEXT:    addiu $2, $zero, 0
 ;
 ; GP64-LABEL: srem_i1:
 ; GP64:       # %bb.0: # %entry
-; GP64-NEXT:    div $zero, $4, $5
-; GP64-NEXT:    teq $5, $zero, 7
-; GP64-NEXT:    mfhi $1
-; GP64-NEXT:    andi $1, $1, 1
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    negu $2, $1
+; GP64-NEXT:    addiu $2, $zero, 0
 ;
 ; GP64R6-LABEL: srem_i1:
 ; GP64R6:       # %bb.0: # %entry
-; GP64R6-NEXT:    mod $1, $4, $5
-; GP64R6-NEXT:    teq $5, $zero, 7
-; GP64R6-NEXT:    andi $1, $1, 1
 ; GP64R6-NEXT:    jr $ra
-; GP64R6-NEXT:    negu $2, $1
+; GP64R6-NEXT:    addiu $2, $zero, 0
 ;
 ; MMR3-LABEL: srem_i1:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    div $zero, $4, $5
-; MMR3-NEXT:    teq $5, $zero, 7
-; MMR3-NEXT:    mfhi16 $2
-; MMR3-NEXT:    andi16 $2, $2, 1
-; MMR3-NEXT:    li16 $3, 0
-; MMR3-NEXT:    subu16 $2, $3, $2
+; MMR3-NEXT:    li16 $2, 0
 ; MMR3-NEXT:    jrc $ra
 ;
 ; MMR6-LABEL: srem_i1:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    mod $2, $4, $5
-; MMR6-NEXT:    teq $5, $zero, 7
-; MMR6-NEXT:    andi16 $2, $2, 1
-; MMR6-NEXT:    li16 $3, 0
-; MMR6-NEXT:    subu16 $2, $3, $2
+; MMR6-NEXT:    li16 $2, 0
 ; MMR6-NEXT:    jrc $ra
 entry:
   %r = srem i1 %a, %b

llvm/test/CodeGen/Mips/llvm-ir/udiv.ll

@@ -35,41 +35,32 @@
 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
 ; GP32-LABEL: udiv_i1:
 ; GP32:       # %bb.0: # %entry
-; GP32-NEXT:    divu $zero, $4, $5
-; GP32-NEXT:    teq $5, $zero, 7
 ; GP32-NEXT:    jr $ra
-; GP32-NEXT:    mflo $2
+; GP32-NEXT:    move $2, $4
 ;
 ; GP32R6-LABEL: udiv_i1:
 ; GP32R6:       # %bb.0: # %entry
-; GP32R6-NEXT:    divu $2, $4, $5
-; GP32R6-NEXT:    teq $5, $zero, 7
-; GP32R6-NEXT:    jrc $ra
+; GP32R6-NEXT:    jr $ra
+; GP32R6-NEXT:    move $2, $4
 ;
 ; GP64-LABEL: udiv_i1:
 ; GP64:       # %bb.0: # %entry
-; GP64-NEXT:    divu $zero, $4, $5
-; GP64-NEXT:    teq $5, $zero, 7
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    mflo $2
+; GP64-NEXT:    move $2, $4
 ;
 ; GP64R6-LABEL: udiv_i1:
 ; GP64R6:       # %bb.0: # %entry
-; GP64R6-NEXT:    divu $2, $4, $5
-; GP64R6-NEXT:    teq $5, $zero, 7
-; GP64R6-NEXT:    jrc $ra
+; GP64R6-NEXT:    jr $ra
+; GP64R6-NEXT:    move $2, $4
 ;
 ; MMR3-LABEL: udiv_i1:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    divu $zero, $4, $5
-; MMR3-NEXT:    teq $5, $zero, 7
-; MMR3-NEXT:    mflo16 $2
+; MMR3-NEXT:    move $2, $4
 ; MMR3-NEXT:    jrc $ra
 ;
 ; MMR6-LABEL: udiv_i1:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    divu $2, $4, $5
-; MMR6-NEXT:    teq $5, $zero, 7
+; MMR6-NEXT:    move $2, $4
 ; MMR6-NEXT:    jrc $ra
 entry:
   %r = udiv i1 %a, %b

llvm/test/CodeGen/Mips/llvm-ir/urem.ll

@@ -35,64 +35,32 @@
 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
 ; GP32-LABEL: urem_i1:
 ; GP32:       # %bb.0: # %entry
-; GP32-NEXT:    andi $1, $5, 1
-; GP32-NEXT:    andi $2, $4, 1
-; GP32-NEXT:    divu $zero, $2, $1
-; GP32-NEXT:    teq $1, $zero, 7
-; GP32-NEXT:    mfhi $1
-; GP32-NEXT:    andi $1, $1, 1
 ; GP32-NEXT:    jr $ra
-; GP32-NEXT:    negu $2, $1
+; GP32-NEXT:    addiu $2, $zero, 0
 ;
 ; GP32R6-LABEL: urem_i1:
 ; GP32R6:       # %bb.0: # %entry
-; GP32R6-NEXT:    andi $1, $5, 1
-; GP32R6-NEXT:    andi $2, $4, 1
-; GP32R6-NEXT:    modu $2, $2, $1
-; GP32R6-NEXT:    teq $1, $zero, 7
 ; GP32R6-NEXT:    jr $ra
-; GP32R6-NEXT:    negu $2, $2
+; GP32R6-NEXT:    addiu $2, $zero, 0
 ;
 ; GP64-LABEL: urem_i1:
 ; GP64:       # %bb.0: # %entry
-; GP64-NEXT:    andi $1, $5, 1
-; GP64-NEXT:    andi $2, $4, 1
-; GP64-NEXT:    divu $zero, $2, $1
-; GP64-NEXT:    teq $1, $zero, 7
-; GP64-NEXT:    mfhi $1
-; GP64-NEXT:    andi $1, $1, 1
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    negu $2, $1
+; GP64-NEXT:    addiu $2, $zero, 0
 ;
 ; GP64R6-LABEL: urem_i1:
 ; GP64R6:       # %bb.0: # %entry
-; GP64R6-NEXT:    andi $1, $5, 1
-; GP64R6-NEXT:    andi $2, $4, 1
-; GP64R6-NEXT:    modu $2, $2, $1
-; GP64R6-NEXT:    teq $1, $zero, 7
 ; GP64R6-NEXT:    jr $ra
-; GP64R6-NEXT:    negu $2, $2
+; GP64R6-NEXT:    addiu $2, $zero, 0
 ;
 ; MMR3-LABEL: urem_i1:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    andi16 $2, $5, 1
-; MMR3-NEXT:    andi16 $3, $4, 1
-; MMR3-NEXT:    divu $zero, $3, $2
-; MMR3-NEXT:    teq $2, $zero, 7
-; MMR3-NEXT:    mfhi16 $2
-; MMR3-NEXT:    andi16 $2, $2, 1
-; MMR3-NEXT:    li16 $3, 0
-; MMR3-NEXT:    subu16 $2, $3, $2
+; MMR3-NEXT:    li16 $2, 0
 ; MMR3-NEXT:    jrc $ra
 ;
 ; MMR6-LABEL: urem_i1:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    andi16 $2, $5, 1
-; MMR6-NEXT:    andi16 $3, $4, 1
-; MMR6-NEXT:    modu $3, $3, $2
-; MMR6-NEXT:    teq $2, $zero, 7
 ; MMR6-NEXT:    li16 $2, 0
-; MMR6-NEXT:    subu16 $2, $2, $3
 ; MMR6-NEXT:    jrc $ra
 entry:
   %r = urem i1 %a, %b