[PR] Add AARCH64_MOVW_UABS_G* relocations support

Summary: This patch fixes issue facebookarchive/BOLT#177 Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei (cherry picked from FBD31130162)
llvm · Sep 22, 2021 · e1da153 · e1da153
1 parent d4fdc98
commit e1da153
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diff --git a/bolt/src/BinaryFunction.h b/bolt/src/BinaryFunction.h
@@ -1307,6 +1307,13 @@ class BinaryFunction {
     case ELF::R_AARCH64_TLSDESC_LD64_LO12:
     case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
     case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+    case ELF::R_AARCH64_MOVW_UABS_G0:
+    case ELF::R_AARCH64_MOVW_UABS_G0_NC:
+    case ELF::R_AARCH64_MOVW_UABS_G1:
+    case ELF::R_AARCH64_MOVW_UABS_G1_NC:
+    case ELF::R_AARCH64_MOVW_UABS_G2:
+    case ELF::R_AARCH64_MOVW_UABS_G2_NC:
+    case ELF::R_AARCH64_MOVW_UABS_G3:
       Relocations[Offset] = Relocation{Offset, Symbol, RelType, Addend, Value};
       return;
     case ELF::R_AARCH64_CALL26:

diff --git a/bolt/src/Relocation.cpp b/bolt/src/Relocation.cpp
@@ -69,6 +69,13 @@ bool isSupportedAArch64(uint64_t Type) {
   case ELF::R_AARCH64_JUMP26:
   case ELF::R_AARCH64_PREL32:
   case ELF::R_AARCH64_ABS64:
+  case ELF::R_AARCH64_MOVW_UABS_G0:
+  case ELF::R_AARCH64_MOVW_UABS_G0_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G1:
+  case ELF::R_AARCH64_MOVW_UABS_G1_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G2:
+  case ELF::R_AARCH64_MOVW_UABS_G2_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G3:
     return true;
   }
 }
@@ -126,6 +133,13 @@ size_t getSizeForTypeAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
   case ELF::R_AARCH64_JUMP26:
   case ELF::R_AARCH64_PREL32:
+  case ELF::R_AARCH64_MOVW_UABS_G0:
+  case ELF::R_AARCH64_MOVW_UABS_G0_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G1:
+  case ELF::R_AARCH64_MOVW_UABS_G1_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G2:
+  case ELF::R_AARCH64_MOVW_UABS_G2_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G3:
     return 4;
   case ELF::R_AARCH64_ABS64:
     return 8;
@@ -280,6 +294,18 @@ uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents, uint64_t PC) {
     Contents &= ~0xffffffffffc003ffU;
     return Contents >> (10 - 0);
   }
+  case ELF::R_AARCH64_MOVW_UABS_G3:
+  case ELF::R_AARCH64_MOVW_UABS_G2_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G2:
+  case ELF::R_AARCH64_MOVW_UABS_G1_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G1:
+  case ELF::R_AARCH64_MOVW_UABS_G0_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G0:
+    // The shift goest in bits 22:21 of MOV* instructions
+    uint8_t Shift = (Contents >> 21) & 0x3;
+    // Immediate goes in bits 20:5
+    Contents = (Contents >> 5) & 0xffff;
+    return Contents << (16 * Shift);
   }
 }
 
@@ -388,6 +414,13 @@ bool isPCRelativeAArch64(uint64_t Type) {
   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
+  case ELF::R_AARCH64_MOVW_UABS_G0:
+  case ELF::R_AARCH64_MOVW_UABS_G0_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G1:
+  case ELF::R_AARCH64_MOVW_UABS_G1_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G2:
+  case ELF::R_AARCH64_MOVW_UABS_G2_NC:
+  case ELF::R_AARCH64_MOVW_UABS_G3:
     return false;
   case ELF::R_AARCH64_TLSDESC_CALL:
   case ELF::R_AARCH64_CALL26:

diff --git a/bolt/src/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/src/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -347,6 +347,17 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
       case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
       case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
         return AArch64MCExpr::create(Expr, AArch64MCExpr::VK_LO12, Ctx);
+      case ELF::R_AARCH64_MOVW_UABS_G3:
+        return AArch64MCExpr::create(Expr, AArch64MCExpr::VK_ABS_G3, Ctx);
+      case ELF::R_AARCH64_MOVW_UABS_G2:
+      case ELF::R_AARCH64_MOVW_UABS_G2_NC:
+        return AArch64MCExpr::create(Expr, AArch64MCExpr::VK_ABS_G2_NC, Ctx);
+      case ELF::R_AARCH64_MOVW_UABS_G1:
+      case ELF::R_AARCH64_MOVW_UABS_G1_NC:
+        return AArch64MCExpr::create(Expr, AArch64MCExpr::VK_ABS_G1_NC, Ctx);
+      case ELF::R_AARCH64_MOVW_UABS_G0:
+      case ELF::R_AARCH64_MOVW_UABS_G0_NC:
+        return AArch64MCExpr::create(Expr, AArch64MCExpr::VK_ABS_G0_NC, Ctx);
       default:
         break;
       }

diff --git a/bolt/test/AArch64/issue177.s b/bolt/test/AArch64/issue177.s
@@ -0,0 +1,28 @@
+# This reproduces issue 177 from our github repo
+# AARCH64_MOVW_UABS_G* relocations handling
+
+# REQUIRES: system-linux
+
+# RUN: %host_cc %cflags -no-pie %s -o %t.exe -Wl,-q
+# RUN: llvm-bolt %t.exe -o %t.bolt -use-old-text=0 -lite=0 -trap-old-code
+# RUN: %t.bolt
+
+.text
+.align 4
+.global test
+.type test, %function
+test:
+mov x0, xzr
+ret
+.size test, .-test
+
+.align 4
+.global main
+.type main, %function
+main:
+movz x0, #:abs_g3:test
+movk x0, #:abs_g2_nc:test
+movk x0, #:abs_g1_nc:test
+movk x0, #:abs_g0_nc:test
+br x0
+.size main, .-main