[AMDGPU] fix readlane/readfirstlane src vgpr operand type.

For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand).
readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).

Differential Revision: http://reviews.llvm.org/D18696

llvm-svn: 265670

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -1205,7 +1205,7 @@ let Uses = [EXEC] in {
 def V_READFIRSTLANE_B32 : VOP1 <
   0x00000002,
   (outs SReg_32:$vdst),
-  (ins VGPR_32:$src0),
+  (ins VS_32:$src0),
   "v_readfirstlane_b32 $vdst, $src0",
   []
 >;
@@ -1579,7 +1579,7 @@ defm V_READLANE_B32 : VOP2SI_3VI_m <
   vop3 <0x001, 0x289>,
   "v_readlane_b32",
   (outs SReg_32:$vdst),
-  (ins VGPR_32:$src0, SCSrc_32:$src1),
+  (ins VS_32:$src0, SCSrc_32:$src1),
   "v_readlane_b32 $vdst, $src0, $src1"
 >;
 

llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt

@@ -3,6 +3,9 @@
 # VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e
 
+# VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
+0x02 0x05 0x02 0x7e
+
 # VI:   v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e]
 0x02 0x37 0x02 0x7e
 

llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt

@@ -1,7 +1,7 @@
 # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
 
-# FIXME:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
-#0x01 0x00 0x89 0xd2 0x02 0x07 0x00 0x00
+# VI:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
+0x01 0x00 0x89 0xd2 0x02 0x07 0x00 0x00
 
 # VI:   v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00]
 0x01 0x00 0x8a 0xd2 0x02 0x06 0x00 0x00