AVX512:Implemented encoding for the vmovq.s instruction.

Differential Revision: http://reviews.llvm.org/D14810 llvm-svn: 254248
llvm · Nov 29, 2015 · e293e83 · e293e83
1 parent 3a71f35
commit e293e83
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diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -2913,6 +2913,11 @@ def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
                        EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
                        Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
 
+def VMOV64toPQIZrr_REV : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
+                            (ins VR128X:$src),
+                            "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
+                            EVEX, VEX_W, VEX_LIG;
+
 // Move Scalar Single to Double Int
 //
 let isCodeGenOnly = 1 in {

diff --git a/llvm/test/MC/X86/avx512-encodings.s b/llvm/test/MC/X86/avx512-encodings.s
@@ -19077,3 +19077,19 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
 // CHECK:  encoding: [0x62,0x81,0x7c,0xce,0x11,0xe3]
           vmovups.s %zmm20, %zmm27 {%k6} {z}
 
+// CHECK: vmovq.s %xmm9, %xmm29
+// CHECK:  encoding: [0x62,0x11,0xfd,0x08,0xd6,0xcd]
+          vmovq.s %xmm9, %xmm29
+
+// CHECK: vmovq.s %xmm5, %xmm18
+// CHECK:  encoding: [0x62,0xb1,0xfd,0x08,0xd6,0xea]
+          vmovq.s %xmm5, %xmm18
+
+// CHECK: vmovq.s  %xmm14, %xmm25
+// CHECK:  encoding: [0x62,0x11,0xfd,0x08,0xd6,0xf1]
+          vmovq.s  %xmm14, %xmm25
+
+// CHECK: vmovq.s  %xmm24, %xmm12
+// CHECK:  encoding: [0x62,0x41,0xfd,0x08,0xd6,0xc4]
+          vmovq.s  %xmm24, %xmm12
+