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[AMDGPU] Use correct number of bits needed for div/rem shrinking (#80622
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)

There was an error where dividend of type i64 and actual used number of
bits of 32 fell into path that assumes only 24 bits being used. Check
that AtLeast field is used correctly when using computeNumSignBits and
add necessary extend/trunc for 32 bits path.

Regolden and update testcases.

@jrbyrnes @bcahoon @arsenm @rampitec
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@choikwa
choikwa committed Feb 6, 2024
1 parent 9ea34be commit e5638c5
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Showing 11 changed files with 1,158 additions and 858 deletions.
21 changes: 12 additions & 9 deletions llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1213,7 +1213,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder,
BinaryOperator &I, Value *Num,
Value *Den, bool IsDiv,
bool IsSigned) const {
int DivBits = getDivNumBits(I, Num, Den, 9, IsSigned);
unsigned SSBits = Num->getType()->getScalarSizeInBits();
// If Num bits <= 24, assume 0 signbits.
unsigned AtLeast = (SSBits <= 24) ? 0 : (SSBits - 24 + IsSigned);
int DivBits = getDivNumBits(I, Num, Den, AtLeast, IsSigned);
if (DivBits == -1)
return nullptr;
return expandDivRem24Impl(Builder, I, Num, Den, DivBits, IsDiv, IsSigned);
Expand Down Expand Up @@ -1385,13 +1388,13 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder,
Type *I32Ty = Builder.getInt32Ty();
Type *F32Ty = Builder.getFloatTy();

if (Ty->getScalarSizeInBits() < 32) {
if (Ty->getScalarSizeInBits() != 32) {
if (IsSigned) {
X = Builder.CreateSExt(X, I32Ty);
Y = Builder.CreateSExt(Y, I32Ty);
X = Builder.CreateSExtOrTrunc(X, I32Ty);
Y = Builder.CreateSExtOrTrunc(Y, I32Ty);
} else {
X = Builder.CreateZExt(X, I32Ty);
Y = Builder.CreateZExt(Y, I32Ty);
X = Builder.CreateZExtOrTrunc(X, I32Ty);
Y = Builder.CreateZExtOrTrunc(Y, I32Ty);
}
}

Expand Down Expand Up @@ -1482,10 +1485,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder,
if (IsSigned) {
Res = Builder.CreateXor(Res, Sign);
Res = Builder.CreateSub(Res, Sign);
Res = Builder.CreateSExtOrTrunc(Res, Ty);
} else {
Res = Builder.CreateZExtOrTrunc(Res, Ty);
}

Res = Builder.CreateTrunc(Res, Ty);

return Res;
}

Expand Down
104 changes: 67 additions & 37 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3055,19 +3055,29 @@ define i64 @v_sdiv_i64_24bit(i64 %num, i64 %den) {
; CGP-LABEL: v_sdiv_i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0
; CGP-NEXT: v_rcp_f32_e32 v2, v1
; CGP-NEXT: v_mul_f32_e32 v2, v0, v2
; CGP-NEXT: v_trunc_f32_e32 v2, v2
; CGP-NEXT: v_mad_f32 v0, -v2, v1, v0
; CGP-NEXT: v_cvt_i32_f32_e32 v2, v2
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
; CGP-NEXT: v_and_b32_e32 v5, 0xffffff, v0
; CGP-NEXT: v_rcp_f32_e32 v1, v1
; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v1
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v3
; CGP-NEXT: v_mul_lo_u32 v1, v1, v4
; CGP-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v1, 0
; CGP-NEXT: v_mov_b32_e32 v0, v2
; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v0, 0
; CGP-NEXT: v_mov_b32_e32 v0, v1
; CGP-NEXT: v_mul_lo_u32 v1, v0, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v5, v1
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CGP-NEXT: s_setpc_b64 s[30:31]
%num.mask = and i64 %num, 16777215
Expand Down Expand Up @@ -3335,32 +3345,52 @@ define <2 x i64> @v_sdiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; CGP-LABEL: v_sdiv_v2i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4
; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
; CGP-NEXT: v_and_b32_e32 v4, 0xffffff, v6
; CGP-NEXT: v_rcp_f32_e32 v3, v1
; CGP-NEXT: v_cvt_f32_i32_e32 v4, v4
; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v3
; CGP-NEXT: v_rcp_f32_e32 v1, v1
; CGP-NEXT: v_and_b32_e32 v7, 0xffffff, v0
; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_i32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v3, v0, v3
; CGP-NEXT: v_trunc_f32_e32 v3, v3
; CGP-NEXT: v_mad_f32 v0, -v3, v1, v0
; CGP-NEXT: v_cvt_i32_f32_e32 v3, v3
; CGP-NEXT: v_rcp_f32_e32 v5, v4
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0
; CGP-NEXT: v_mul_f32_e32 v3, v2, v5
; CGP-NEXT: v_trunc_f32_e32 v3, v3
; CGP-NEXT: v_mad_f32 v2, -v3, v4, v2
; CGP-NEXT: v_cvt_i32_f32_e32 v3, v3
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v4|
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CGP-NEXT: v_bfe_i32 v2, v2, 0, 25
; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v4
; CGP-NEXT: v_mul_lo_u32 v6, v6, v5
; CGP-NEXT: v_rcp_f32_e32 v8, v1
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v6, 0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v0
; CGP-NEXT: v_mov_b32_e32 v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v5, v0
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v0, 0
; CGP-NEXT: v_sub_i32_e32 v0, vcc, 0, v4
; CGP-NEXT: v_mov_b32_e32 v5, v1
; CGP-NEXT: v_mul_lo_u32 v0, v0, v6
; CGP-NEXT: v_mul_lo_u32 v1, v5, v3
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v5
; CGP-NEXT: v_sub_i32_e32 v7, vcc, v7, v1
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v0, 0
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; CGP-NEXT: v_mov_b32_e32 v0, v1
; CGP-NEXT: v_add_i32_e64 v0, s[4:5], v6, v0
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0
; CGP-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc
; CGP-NEXT: v_mov_b32_e32 v7, v1
; CGP-NEXT: v_mul_lo_u32 v8, v7, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v5
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v7
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; CGP-NEXT: s_setpc_b64 s[30:31]
Expand Down
104 changes: 60 additions & 44 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3000,21 +3000,27 @@ define i64 @v_srem_i64_24bit(i64 %num, i64 %den) {
; CGP-LABEL: v_srem_i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_i32_e32 v2, v1
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v3, v0
; CGP-NEXT: v_rcp_f32_e32 v4, v2
; CGP-NEXT: v_mul_f32_e32 v4, v3, v4
; CGP-NEXT: v_trunc_f32_e32 v4, v4
; CGP-NEXT: v_mad_f32 v3, -v4, v2, v3
; CGP-NEXT: v_cvt_i32_f32_e32 v4, v4
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; CGP-NEXT: v_mul_lo_u32 v1, v2, v1
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
; CGP-NEXT: v_and_b32_e32 v5, 0xffffff, v0
; CGP-NEXT: v_rcp_f32_e32 v1, v1
; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v1
; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v3
; CGP-NEXT: v_mul_lo_u32 v1, v1, v4
; CGP-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v1, 0
; CGP-NEXT: v_mov_b32_e32 v0, v2
; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v0, 0
; CGP-NEXT: v_mov_b32_e32 v0, v1
; CGP-NEXT: v_mul_lo_u32 v0, v0, v3
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v5, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CGP-NEXT: s_setpc_b64 s[30:31]
%num.mask = and i64 %num, 16777215
Expand Down Expand Up @@ -3282,37 +3288,47 @@ define <2 x i64> @v_srem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) {
; CGP-LABEL: v_srem_v2i64_24bit:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4
; CGP-NEXT: v_cvt_f32_i32_e32 v3, v1
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_cvt_f32_i32_e32 v4, v0
; CGP-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; CGP-NEXT: v_rcp_f32_e32 v5, v3
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3
; CGP-NEXT: v_and_b32_e32 v4, 0xffffff, v6
; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v3
; CGP-NEXT: v_rcp_f32_e32 v1, v1
; CGP-NEXT: v_and_b32_e32 v7, 0xffffff, v0
; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; CGP-NEXT: v_mul_f32_e32 v5, v4, v5
; CGP-NEXT: v_trunc_f32_e32 v5, v5
; CGP-NEXT: v_mad_f32 v4, -v5, v3, v4
; CGP-NEXT: v_cvt_i32_f32_e32 v5, v5
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, |v3|
; CGP-NEXT: v_cvt_f32_i32_e32 v4, v6
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CGP-NEXT: v_mul_lo_u32 v1, v3, v1
; CGP-NEXT: v_cvt_f32_i32_e32 v3, v2
; CGP-NEXT: v_rcp_f32_e32 v5, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_mul_f32_e32 v1, v3, v5
; CGP-NEXT: v_trunc_f32_e32 v1, v1
; CGP-NEXT: v_mad_f32 v3, -v1, v4, v3
; CGP-NEXT: v_cvt_i32_f32_e32 v1, v1
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v4|
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CGP-NEXT: v_mul_lo_u32 v3, v1, v6
; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v4
; CGP-NEXT: v_mul_lo_u32 v6, v6, v5
; CGP-NEXT: v_rcp_f32_e32 v8, v1
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v6, 0
; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v0
; CGP-NEXT: v_mov_b32_e32 v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v5, v0
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v0, 0
; CGP-NEXT: v_sub_i32_e32 v0, vcc, 0, v4
; CGP-NEXT: v_mul_lo_u32 v0, v0, v6
; CGP-NEXT: v_mul_lo_u32 v5, v1, v3
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v0, 0
; CGP-NEXT: v_sub_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mov_b32_e32 v0, v1
; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0
; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0
; CGP-NEXT: v_sub_i32_e32 v7, vcc, v5, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3
; CGP-NEXT: v_mul_lo_u32 v6, v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
; CGP-NEXT: v_sub_i32_e32 v5, vcc, v0, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_bfe_i32 v2, v2, 0, 25
; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; CGP-NEXT: s_setpc_b64 s[30:31]
%num.mask = and <2 x i64> %num, <i64 16777215, i64 16777215>
Expand Down
86 changes: 31 additions & 55 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -415,25 +415,17 @@ define i32 @v_udiv_i32_24bit(i32 %num, i32 %den) {
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; CGP-NEXT: v_rcp_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1
; CGP-NEXT: v_rcp_f32_e32 v2, v1
; CGP-NEXT: v_mul_f32_e32 v2, v0, v2
; CGP-NEXT: v_trunc_f32_e32 v2, v2
; CGP-NEXT: v_fma_f32 v0, -v2, v1, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v2, v0, v2
; CGP-NEXT: v_mul_lo_u32 v3, v2, v1
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v2
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v1
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: s_setpc_b64 s[30:31]
%num.mask = and i32 %num, 16777215
%den.mask = and i32 %den, 16777215
Expand Down Expand Up @@ -496,44 +488,28 @@ define <2 x i32> @v_udiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
; CGP-NEXT: v_rcp_f32_e32 v4, v4
; CGP-NEXT: v_rcp_f32_e32 v6, v6
; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v3
; CGP-NEXT: v_rcp_f32_e32 v4, v2
; CGP-NEXT: v_rcp_f32_e32 v5, v3
; CGP-NEXT: v_mul_f32_e32 v4, v0, v4
; CGP-NEXT: v_mul_f32_e32 v5, v1, v5
; CGP-NEXT: v_trunc_f32_e32 v4, v4
; CGP-NEXT: v_trunc_f32_e32 v5, v5
; CGP-NEXT: v_fma_f32 v0, -v4, v2, v0
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
; CGP-NEXT: v_mul_lo_u32 v5, v5, v4
; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
; CGP-NEXT: v_mul_hi_u32 v5, v4, v5
; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7
; CGP-NEXT: v_mul_hi_u32 v4, v0, v4
; CGP-NEXT: v_mul_hi_u32 v5, v1, v5
; CGP-NEXT: v_mul_lo_u32 v6, v4, v2
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; CGP-NEXT: v_mul_lo_u32 v8, v5, v3
; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3
; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
; CGP-NEXT: v_fma_f32 v1, -v5, v3, v1
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v2
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, v3
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; CGP-NEXT: s_setpc_b64 s[30:31]
%num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>
%den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>
Expand Down

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