[Test] Add data layout to relevant tests + some wide-typed tests

llvm · Jan 27, 2022 · e74d146 · e74d146
1 parent c4e6895
commit e74d146
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diff --git a/llvm/test/Transforms/InstCombine/icmp-vec.ll b/llvm/test/Transforms/InstCombine/icmp-vec.ll
@@ -6,6 +6,8 @@
 ; Normal types are ConstantDataVectors. Test the constant values adjacent to the
 ; min/max values that we're not allowed to transform.
 
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
 define <2 x i1> @sge(<2 x i8> %x) {
 ; CHECK-LABEL: @sge(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 -128, i8 126>

diff --git a/llvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
 define i1 @reduce_and_self(<8 x i1> %x) {
 ; CHECK-LABEL: @reduce_and_self(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
@@ -117,6 +119,28 @@ bb:
   ret i1 %all_eq
 }
 
+define i1 @reduce_and_pointer_cast_wide(i8* %arg, i8* %arg1) {
+; CHECK-LABEL: @reduce_and_pointer_cast_wide(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[PTR1:%.*]] = bitcast i8* [[ARG1:%.*]] to <8 x i16>*
+; CHECK-NEXT:    [[PTR2:%.*]] = bitcast i8* [[ARG:%.*]] to <8 x i16>*
+; CHECK-NEXT:    [[LHS:%.*]] = load <8 x i16>, <8 x i16>* [[PTR1]], align 16
+; CHECK-NEXT:    [[RHS:%.*]] = load <8 x i16>, <8 x i16>* [[PTR2]], align 16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne <8 x i16> [[LHS]], [[RHS]]
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i1> [[CMP]] to i8
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[TMP0]], 0
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+bb:
+  %ptr1 = bitcast i8* %arg1 to <8 x i16>*
+  %ptr2 = bitcast i8* %arg to <8 x i16>*
+  %lhs = load <8 x i16>, <8 x i16>* %ptr1
+  %rhs = load <8 x i16>, <8 x i16>* %ptr2
+  %cmp = icmp eq <8 x i16> %lhs, %rhs
+  %all_eq = call i1 @llvm.vector.reduce.and.v8i32(<8 x i1> %cmp)
+  ret i1 %all_eq
+}
+
 declare i1 @llvm.vector.reduce.and.v8i32(<8 x i1> %a)
 declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
 declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %a)

diff --git a/llvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
 define i1 @reduce_or_self(<8 x i1> %x) {
 ; CHECK-LABEL: @reduce_or_self(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
@@ -118,6 +120,29 @@ bb:
   ret i1 %all_eq
 }
 
+define i1 @reduce_or_pointer_cast_wide(i8* %arg, i8* %arg1) {
+; CHECK-LABEL: @reduce_or_pointer_cast_wide(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[PTR1:%.*]] = bitcast i8* [[ARG1:%.*]] to <8 x i16>*
+; CHECK-NEXT:    [[PTR2:%.*]] = bitcast i8* [[ARG:%.*]] to <8 x i16>*
+; CHECK-NEXT:    [[LHS:%.*]] = load <8 x i16>, <8 x i16>* [[PTR1]], align 16
+; CHECK-NEXT:    [[RHS:%.*]] = load <8 x i16>, <8 x i16>* [[PTR2]], align 16
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne <8 x i16> [[LHS]], [[RHS]]
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i1> [[CMP]] to i8
+; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i8 [[TMP0]], 0
+; CHECK-NEXT:    ret i1 [[DOTNOT]]
+;
+bb:
+  %ptr1 = bitcast i8* %arg1 to <8 x i16>*
+  %ptr2 = bitcast i8* %arg to <8 x i16>*
+  %lhs = load <8 x i16>, <8 x i16>* %ptr1
+  %rhs = load <8 x i16>, <8 x i16>* %ptr2
+  %cmp = icmp ne <8 x i16> %lhs, %rhs
+  %any_ne = call i1 @llvm.vector.reduce.or.v8i32(<8 x i1> %cmp)
+  %all_eq = xor i1 %any_ne, 1
+  ret i1 %all_eq
+}
+
 declare i1 @llvm.vector.reduce.or.v8i32(<8 x i1> %a)
 declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
 declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %a)