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This folds (ashr (shl a, [56,48,32,24,16]), SarConst) into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or into (lshr, (sext (a), SarConst - [56,48,32,24,16])) depending on sign of (SarConst - [56,48,32,24,16]) sexts in X86 are MOVs. The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size). However the MOVs have 2 advantages to SHIFTs on x86: 1. MOVs can write to a register that differs from source. 2. MOVs accept memory operands. This fixes PR24373. Patch by: evgeny.v.stupachenko@intel.com Differential Revision: http://reviews.llvm.org/D13161 llvm-svn: 255761
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Michael Kuperstein
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Dec 16, 2015
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,37 @@ | ||
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s | ||
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define i32 @shl16sar15(i32 %a) #0 { | ||
; CHECK-LABEL: shl16sar15: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movswl {{[0-9]+}}(%esp), %eax | ||
%1 = shl i32 %a, 16 | ||
%2 = ashr exact i32 %1, 15 | ||
ret i32 %2 | ||
} | ||
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define i32 @shl16sar17(i32 %a) #0 { | ||
; CHECK-LABEL: shl16sar17: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movswl {{[0-9]+}}(%esp), %eax | ||
%1 = shl i32 %a, 16 | ||
%2 = ashr exact i32 %1, 17 | ||
ret i32 %2 | ||
} | ||
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define i32 @shl24sar23(i32 %a) #0 { | ||
; CHECK-LABEL: shl24sar23: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movsbl {{[0-9]+}}(%esp), %eax | ||
%1 = shl i32 %a, 24 | ||
%2 = ashr exact i32 %1, 23 | ||
ret i32 %2 | ||
} | ||
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define i32 @shl24sar25(i32 %a) #0 { | ||
; CHECK-LABEL: shl24sar25: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movsbl {{[0-9]+}}(%esp), %eax | ||
%1 = shl i32 %a, 24 | ||
%2 = ashr exact i32 %1, 25 | ||
ret i32 %2 | ||
} |
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@@ -0,0 +1,43 @@ | ||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s | ||
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define i32 @shl48sar47(i64 %a) #0 { | ||
; CHECK-LABEL: shl48sar47: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movswq %di, %rax | ||
%1 = shl i64 %a, 48 | ||
%2 = ashr exact i64 %1, 47 | ||
%3 = trunc i64 %2 to i32 | ||
ret i32 %3 | ||
} | ||
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define i32 @shl48sar49(i64 %a) #0 { | ||
; CHECK-LABEL: shl48sar49: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movswq %di, %rax | ||
%1 = shl i64 %a, 48 | ||
%2 = ashr exact i64 %1, 49 | ||
%3 = trunc i64 %2 to i32 | ||
ret i32 %3 | ||
} | ||
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define i32 @shl56sar55(i64 %a) #0 { | ||
; CHECK-LABEL: shl56sar55: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movsbq %dil, %rax | ||
%1 = shl i64 %a, 56 | ||
%2 = ashr exact i64 %1, 55 | ||
%3 = trunc i64 %2 to i32 | ||
ret i32 %3 | ||
} | ||
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define i32 @shl56sar57(i64 %a) #0 { | ||
; CHECK-LABEL: shl56sar57: | ||
; CHECK: # BB#0: | ||
; CHECK-NEXT: movsbq %dil, %rax | ||
%1 = shl i64 %a, 56 | ||
%2 = ashr exact i64 %1, 57 | ||
%3 = trunc i64 %2 to i32 | ||
ret i32 %3 | ||
} | ||
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attributes #0 = { nounwind } |
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