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[AArch64][SVE2] Asm: add integer pairwise arithmetic instructions
Summary: Patch adds support for the following instructions: ADDP, SMAXP, UMAXP, SMINP, UMINP The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62128 llvm-svn: 361229
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s | ||
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// --------------------------------------------------------------------------// | ||
// Source and Destination Registers must match | ||
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addp z0.b, p0/m, z1.b, z2.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register | ||
// CHECK-NEXT: addp z0.b, p0/m, z1.b, z2.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Element sizes must match | ||
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addp z0.b, p0/m, z0.d, z1.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: addp z0.b, p0/m, z0.d, z1.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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addp z0.b, p0/m, z0.b, z1.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: addp z0.b, p0/m, z0.b, z1.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Invalid predicate | ||
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addp z0.b, p0/z, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction | ||
// CHECK-NEXT: addp z0.b, p0/z, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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addp z0.b, p8/m, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. | ||
// CHECK-NEXT: addp z0.b, p8/m, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
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addp z0.b, p0/m, z0.b, z1.b | ||
// CHECK-INST: addp z0.b, p0/m, z0.b, z1.b | ||
// CHECK-ENCODING: [0x20,0xa0,0x11,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 a0 11 44 <unknown> | ||
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addp z0.h, p0/m, z0.h, z1.h | ||
// CHECK-INST: addp z0.h, p0/m, z0.h, z1.h | ||
// CHECK-ENCODING: [0x20,0xa0,0x51,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 a0 51 44 <unknown> | ||
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addp z29.s, p7/m, z29.s, z30.s | ||
// CHECK-INST: addp z29.s, p7/m, z29.s, z30.s | ||
// CHECK-ENCODING: [0xdd,0xbf,0x91,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: dd bf 91 44 <unknown> | ||
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addp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df bf d1 44 <unknown> | ||
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// --------------------------------------------------------------------------// | ||
// Test compatibility with MOVPRFX instruction. | ||
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movprfx z31.d, p0/z, z6.d | ||
// CHECK-INST: movprfx z31.d, p0/z, z6.d | ||
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: df 20 d0 04 <unknown> | ||
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addp z31.d, p0/m, z31.d, z30.d | ||
// CHECK-INST: addp z31.d, p0/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xa3,0xd1,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df a3 d1 44 <unknown> | ||
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movprfx z31, z6 | ||
// CHECK-INST: movprfx z31, z6 | ||
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: df bc 20 04 <unknown> | ||
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addp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df bf d1 44 <unknown> |
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@@ -0,0 +1,37 @@ | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s | ||
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// --------------------------------------------------------------------------// | ||
// Source and Destination Registers must match | ||
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smaxp z0.b, p0/m, z1.b, z2.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register | ||
// CHECK-NEXT: smaxp z0.b, p0/m, z1.b, z2.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Element sizes must match | ||
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smaxp z0.b, p0/m, z0.d, z1.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: smaxp z0.b, p0/m, z0.d, z1.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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smaxp z0.b, p0/m, z0.b, z1.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: smaxp z0.b, p0/m, z0.b, z1.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Invalid predicate | ||
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smaxp z0.b, p0/z, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction | ||
// CHECK-NEXT: smaxp z0.b, p0/z, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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smaxp z0.b, p8/m, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. | ||
// CHECK-NEXT: smaxp z0.b, p8/m, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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@@ -0,0 +1,59 @@ | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
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smaxp z0.b, p0/m, z0.b, z1.b | ||
// CHECK-INST: smaxp z0.b, p0/m, z0.b, z1.b | ||
// CHECK-ENCODING: [0x20,0xa0,0x14,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 a0 14 44 <unknown> | ||
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smaxp z0.h, p0/m, z0.h, z1.h | ||
// CHECK-INST: smaxp z0.h, p0/m, z0.h, z1.h | ||
// CHECK-ENCODING: [0x20,0xa0,0x54,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 a0 54 44 <unknown> | ||
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smaxp z29.s, p7/m, z29.s, z30.s | ||
// CHECK-INST: smaxp z29.s, p7/m, z29.s, z30.s | ||
// CHECK-ENCODING: [0xdd,0xbf,0x94,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: dd bf 94 44 <unknown> | ||
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smaxp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df bf d4 44 <unknown> | ||
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// --------------------------------------------------------------------------// | ||
// Test compatibility with MOVPRFX instruction. | ||
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movprfx z31.d, p0/z, z6.d | ||
// CHECK-INST: movprfx z31.d, p0/z, z6.d | ||
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: df 20 d0 04 <unknown> | ||
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smaxp z31.d, p0/m, z31.d, z30.d | ||
// CHECK-INST: smaxp z31.d, p0/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xa3,0xd4,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df a3 d4 44 <unknown> | ||
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movprfx z31, z6 | ||
// CHECK-INST: movprfx z31, z6 | ||
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: df bc 20 04 <unknown> | ||
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smaxp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df bf d4 44 <unknown> |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,37 @@ | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s | ||
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// --------------------------------------------------------------------------// | ||
// Source and Destination Registers must match | ||
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sminp z0.b, p0/m, z1.b, z2.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register | ||
// CHECK-NEXT: sminp z0.b, p0/m, z1.b, z2.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Element sizes must match | ||
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sminp z0.b, p0/m, z0.d, z1.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: sminp z0.b, p0/m, z0.d, z1.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sminp z0.b, p0/m, z0.b, z1.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: sminp z0.b, p0/m, z0.b, z1.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Invalid predicate | ||
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sminp z0.b, p0/z, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction | ||
// CHECK-NEXT: sminp z0.b, p0/z, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sminp z0.b, p8/m, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. | ||
// CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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@@ -0,0 +1,59 @@ | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ | ||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
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sminp z0.b, p0/m, z0.b, z1.b | ||
// CHECK-INST: sminp z0.b, p0/m, z0.b, z1.b | ||
// CHECK-ENCODING: [0x20,0xa0,0x16,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 a0 16 44 <unknown> | ||
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sminp z0.h, p0/m, z0.h, z1.h | ||
// CHECK-INST: sminp z0.h, p0/m, z0.h, z1.h | ||
// CHECK-ENCODING: [0x20,0xa0,0x56,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: 20 a0 56 44 <unknown> | ||
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sminp z29.s, p7/m, z29.s, z30.s | ||
// CHECK-INST: sminp z29.s, p7/m, z29.s, z30.s | ||
// CHECK-ENCODING: [0xdd,0xbf,0x96,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: dd bf 96 44 <unknown> | ||
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sminp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df bf d6 44 <unknown> | ||
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// --------------------------------------------------------------------------// | ||
// Test compatibility with MOVPRFX instruction. | ||
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movprfx z31.d, p0/z, z6.d | ||
// CHECK-INST: movprfx z31.d, p0/z, z6.d | ||
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: df 20 d0 04 <unknown> | ||
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sminp z31.d, p0/m, z31.d, z30.d | ||
// CHECK-INST: sminp z31.d, p0/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xa3,0xd6,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df a3 d6 44 <unknown> | ||
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movprfx z31, z6 | ||
// CHECK-INST: movprfx z31, z6 | ||
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: df bc 20 04 <unknown> | ||
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sminp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d | ||
// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] | ||
// CHECK-ERROR: instruction requires: sve2 | ||
// CHECK-UNKNOWN: df bf d6 44 <unknown> |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,37 @@ | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s | ||
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// --------------------------------------------------------------------------// | ||
// Source and Destination Registers must match | ||
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umaxp z0.b, p0/m, z1.b, z2.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register | ||
// CHECK-NEXT: umaxp z0.b, p0/m, z1.b, z2.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Element sizes must match | ||
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umaxp z0.b, p0/m, z0.d, z1.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: umaxp z0.b, p0/m, z0.d, z1.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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umaxp z0.b, p0/m, z0.b, z1.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: umaxp z0.b, p0/m, z0.b, z1.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Invalid predicate | ||
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umaxp z0.b, p0/z, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction | ||
// CHECK-NEXT: umaxp z0.b, p0/z, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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umaxp z0.b, p8/m, z0.b, z1.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. | ||
// CHECK-NEXT: umaxp z0.b, p8/m, z0.b, z1.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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