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Revert "[AMDGPU] gfx11 vop3dpp instructions"
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This reverts commit 99a83b1.
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@Sisyph
Sisyph committed Jun 6, 2022
1 parent f617f89 commit eaed07e
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Showing 20 changed files with 244 additions and 977 deletions.
12 changes: 2 additions & 10 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
View file
Expand Up @@ -1296,10 +1296,8 @@ def AMDGPUAsmVariants {
int SDWA9_ID = 3;
string DPP = "DPP";
int DPP_ID = 4;
string VOP3_DPP = "VOP3_DPP";
int VOP3_DPP_ID = 5;
string Disable = "Disable";
int Disable_ID = 6;
int Disable_ID = 5;
}

def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
Expand Down Expand Up @@ -1327,11 +1325,6 @@ def DPPAsmParserVariant : AsmParserVariant {
let Name = AMDGPUAsmVariants.DPP;
}

def VOP3_DPPAsmParserVariant : AsmParserVariant {
let Variant = AMDGPUAsmVariants.VOP3_DPP_ID;
let Name = AMDGPUAsmVariants.VOP3_DPP;
}

def AMDGPU : Target {
// Pull in Instruction Info:
let InstructionSet = AMDGPUInstrInfo;
Expand All @@ -1340,8 +1333,7 @@ def AMDGPU : Target {
VOP3AsmParserVariant,
SDWAAsmParserVariant,
SDWA9AsmParserVariant,
DPPAsmParserVariant,
VOP3_DPPAsmParserVariant];
DPPAsmParserVariant];
let AssemblyWriters = [AMDGPUAsmWriter];
let AllowRegisterRenaming = 1;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
View file
Expand Up @@ -40,7 +40,7 @@ class AMDGPUInst <dag outs, dag ins, string asm = "",
// instructions to not match without killing the whole decode process. It is
// mainly used for ARM, but Tablegen expects this field to exist or it fails
// to build the decode table.
field bits<96> SoftFail = 0;
field bits<64> SoftFail = 0;

let DecoderNamespace = Namespace;

Expand Down
126 changes: 12 additions & 114 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View file
Expand Up @@ -25,7 +25,6 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
Expand Down Expand Up @@ -124,6 +123,12 @@ class AMDGPUOperand : public MCParsedAsmOperand {
ImmTyD16,
ImmTyClampSI,
ImmTyOModSI,
ImmTyDPP8,
ImmTyDppCtrl,
ImmTyDppRowMask,
ImmTyDppBankMask,
ImmTyDppBoundCtrl,
ImmTyDppFi,
ImmTySdwaDstSel,
ImmTySdwaSrc0Sel,
ImmTySdwaSrc1Sel,
Expand All @@ -149,12 +154,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
ImmTyOpSelHi,
ImmTyNegLo,
ImmTyNegHi,
ImmTyDPP8,
ImmTyDppCtrl,
ImmTyDppRowMask,
ImmTyDppBankMask,
ImmTyDppBoundCtrl,
ImmTyDppFi,
ImmTySwizzle,
ImmTyGprIdxMode,
ImmTyHigh,
Expand Down Expand Up @@ -268,14 +267,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);
}

bool isRegOrInlineImmWithInt16InputMods() const {
return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16);
}

bool isRegOrInlineImmWithInt32InputMods() const {
return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32);
}

bool isRegOrImmWithInt64InputMods() const {
return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);
}
Expand All @@ -292,15 +283,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);
}

bool isRegOrInlineImmWithFP16InputMods() const {
return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16);
}

bool isRegOrInlineImmWithFP32InputMods() const {
return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32);
}


bool isVReg() const {
return isRegClass(AMDGPU::VGPR_32RegClassID) ||
isRegClass(AMDGPU::VReg_64RegClassID) ||
Expand Down Expand Up @@ -1763,8 +1745,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
AMDGPUOperand::Ptr defaultFI() const;
void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); }
void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) { cvtVOP3DPP(Inst, Operands, true); }

OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
AMDGPUOperand::ImmTy Type);
Expand Down Expand Up @@ -3242,19 +3222,14 @@ unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
static ArrayRef<unsigned> getAllVariants() {
static const unsigned Variants[] = {
AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,
AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9,
AMDGPUAsmVariants::DPP, AMDGPUAsmVariants::VOP3_DPP
AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, AMDGPUAsmVariants::DPP
};

return makeArrayRef(Variants);
}

// What asm variants we should check
ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const {
if (isForcedDPP() && isForcedVOP3()) {
static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3_DPP};
return makeArrayRef(Variants);
}
if (getForcedEncodingSize() == 32) {
static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};
return makeArrayRef(Variants);
Expand All @@ -3280,9 +3255,6 @@ ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const {
}

StringRef AMDGPUAsmParser::getMatchedVariantName() const {
if (isForcedDPP() && isForcedVOP3())
return "e64_dpp";

if (getForcedEncodingSize() == 32)
return "e32";

Expand Down Expand Up @@ -5691,11 +5663,7 @@ StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
setForcedDPP(false);
setForcedSDWA(false);

if (Name.endswith("_e64_dpp")) {
setForcedDPP(true);
setForcedEncodingSize(64);
return Name.substr(0, Name.size() - 8);
} else if (Name.endswith("_e64")) {
if (Name.endswith("_e64")) {
setForcedEncodingSize(64);
return Name.substr(0, Name.size() - 4);
} else if (Name.endswith("_e32")) {
Expand Down Expand Up @@ -7863,6 +7831,10 @@ static const OptionalOperand AMDGPUOptionalOperandTable[] = {
{"d16", AMDGPUOperand::ImmTyD16, true, nullptr},
{"dmask", AMDGPUOperand::ImmTyDMask, false, nullptr},
{"dim", AMDGPUOperand::ImmTyDim, false, nullptr},
{"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, nullptr},
{"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, nullptr},
{"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, ConvertBoundCtrl},
{"fi", AMDGPUOperand::ImmTyDppFi, false, nullptr},
{"dst_sel", AMDGPUOperand::ImmTySdwaDstSel, false, nullptr},
{"src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel, false, nullptr},
{"src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel, false, nullptr},
Expand All @@ -7873,12 +7845,6 @@ static const OptionalOperand AMDGPUOptionalOperandTable[] = {
{"op_sel_hi", AMDGPUOperand::ImmTyOpSelHi, false, nullptr},
{"neg_lo", AMDGPUOperand::ImmTyNegLo, false, nullptr},
{"neg_hi", AMDGPUOperand::ImmTyNegHi, false, nullptr},
{"dpp8", AMDGPUOperand::ImmTyDPP8, false, nullptr},
{"dpp_ctrl", AMDGPUOperand::ImmTyDppCtrl, false, nullptr},
{"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, nullptr},
{"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, nullptr},
{"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, ConvertBoundCtrl},
{"fi", AMDGPUOperand::ImmTyDppFi, false, nullptr},
{"blgp", AMDGPUOperand::ImmTyBLGP, false, nullptr},
{"cbsz", AMDGPUOperand::ImmTyCBSZ, false, nullptr},
{"abid", AMDGPUOperand::ImmTyABID, false, nullptr},
Expand Down Expand Up @@ -7949,10 +7915,6 @@ OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands)
res = parseDim(Operands);
} else if (Op.Type == AMDGPUOperand::ImmTyCPol) {
res = parseCPol(Operands);
} else if (Op.Type == AMDGPUOperand::ImmTyDPP8) {
res = parseDPP8(Operands);
} else if (Op.Type == AMDGPUOperand::ImmTyDppCtrl) {
res = parseDPPCtrl(Operands);
} else {
res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);
if (Op.Type == AMDGPUOperand::ImmTyBLGP && res == MatchOperand_NoMatch) {
Expand Down Expand Up @@ -8588,70 +8550,6 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFI() const {
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppFi);
}

void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
OptionalImmIndexMap OptionalIdx;
unsigned Opc = Inst.getOpcode();
bool HasModifiers = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1;
unsigned I = 1;
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
}

int Fi = 0;
for (unsigned E = Operands.size(); I != E; ++I) {
auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),
MCOI::TIED_TO);
if (TiedTo != -1) {
assert((unsigned)TiedTo < Inst.getNumOperands());
// handle tied old or src2 for MAC instructions
Inst.addOperand(Inst.getOperand(TiedTo));
}
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
// Add the register arguments
if (IsDPP8 && Op.isFI()) {
Fi = Op.getImm();
} else if (HasModifiers &&
isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
} else if (Op.isReg()) {
Op.addRegOperands(Inst, 1);
} else if (Op.isImm() &&
Desc.OpInfo[Inst.getNumOperands()].RegClass != -1) {
assert(!HasModifiers && "Case should be unreachable with modifiers");
assert(!Op.IsImmKindLiteral() && "Cannot use literal with DPP");
Op.addImmOperands(Inst, 1);
} else if (Op.isImm()) {
OptionalIdx[Op.getImmTy()] = I;
} else {
llvm_unreachable("unhandled operand type");
}
}
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
}
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
}
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
}

if (IsDPP8) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);
using namespace llvm::AMDGPU::DPP;
Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));
} else {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);
}
}
}

void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
OptionalImmIndexMap OptionalIdx;

Expand Down
26 changes: 0 additions & 26 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
View file
Expand Up @@ -391,17 +391,6 @@ template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
return Res;
}

static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) {
assert(Bytes.size() >= 12);
uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>(
Bytes.data());
Bytes = Bytes.slice(8);
uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>(
Bytes.data());
Bytes = Bytes.slice(4);
return DecoderUInt128(Lo, Hi);
}

// The disassembler is greedy, so we need to check FI operand value to
// not parse a dpp if the correct literal is not set. For dpp16 the
// autogenerated decoder checks the dpp literal
Expand Down Expand Up @@ -432,21 +421,6 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

// Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
// encodings
if (isGFX11Plus() && Bytes.size() >= 12 ) {
DecoderUInt128 DecW = eat12Bytes(Bytes);
Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW,
Address);
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
break;
MI = MCInst(); // clear
Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW,
Address);
if (Res)
break;
}
// Reinitialize Bytes
Bytes = Bytes_.slice(0, MaxInstBytesNum);

if (Bytes.size() >= 8) {
const uint64_t QW = eatBytes<uint64_t>(Bytes);

Expand Down
55 changes: 0 additions & 55 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
View file
Expand Up @@ -15,7 +15,6 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H

#include "llvm/ADT/APInt.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCInst.h"
Expand All @@ -29,60 +28,6 @@ class MCOperand;
class MCSubtargetInfo;
class Twine;

// Exposes an interface expected by autogenerated code in
// FixedLenDecoderEmitter
class DecoderUInt128 {
private:
uint64_t Lo = 0;
uint64_t Hi = 0;

public:
DecoderUInt128() = default;
DecoderUInt128(uint64_t Lo, uint64_t Hi = 0) : Lo(Lo), Hi(Hi) {}
operator bool() const { return Lo || Hi; }
void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits) {
assert(NumBits && NumBits <= 64);
assert(SubBits >> 1 >> (NumBits - 1) == 0);
assert(BitPosition < 128);
if (BitPosition < 64) {
Lo |= SubBits << BitPosition;
Hi |= SubBits >> 1 >> (63 - BitPosition);
} else {
Hi |= SubBits << (BitPosition - 64);
}
}
uint64_t extractBitsAsZExtValue(unsigned NumBits,
unsigned BitPosition) const {
assert(NumBits && NumBits <= 64);
assert(BitPosition < 128);
uint64_t Val;
if (BitPosition < 64)
Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
else
Val = Hi >> (BitPosition - 64);
return Val & ((uint64_t(2) << (NumBits - 1)) - 1);
}
DecoderUInt128 operator&(const DecoderUInt128 &RHS) const {
return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
}
DecoderUInt128 operator&(const uint64_t &RHS) const {
return *this & DecoderUInt128(RHS);
}
DecoderUInt128 operator~() const { return DecoderUInt128(~Lo, ~Hi); }
bool operator==(const DecoderUInt128 &RHS) {
return Lo == RHS.Lo && Hi == RHS.Hi;
}
bool operator!=(const DecoderUInt128 &RHS) {
return Lo != RHS.Lo || Hi != RHS.Hi;
}
bool operator!=(const int &RHS) {
return *this != DecoderUInt128(RHS);
}
friend raw_ostream &operator<<(raw_ostream &OS, const DecoderUInt128 &RHS) {
return OS << APInt(128, {RHS.Lo, RHS.Hi});
}
};

//===----------------------------------------------------------------------===//
// AMDGPUDisassembler
//===----------------------------------------------------------------------===//
Expand Down

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