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[RISCV] Add cost model coverage for mask reductions requiring legaliz…
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@preames
preames committed Jun 10, 2022
1 parent a2cdb97 commit eb91241
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12 changes: 12 additions & 0 deletions llvm/test/Analysis/CostModel/RISCV/reduce-and.ll
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Expand Up @@ -12,6 +12,9 @@ define i32 @reduce_i1(i32 %arg) {
; RISCV32-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 132 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 264 for instruction: %V256 = call i1 @llvm.vector.reduce.and.v256i1(<256 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 528 for instruction: %V512 = call i1 @llvm.vector.reduce.and.v512i1(<512 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 1056 for instruction: %V1024 = call i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
; RISCV64-LABEL: 'reduce_i1'
Expand All @@ -23,6 +26,9 @@ define i32 @reduce_i1(i32 %arg) {
; RISCV64-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %V256 = call i1 @llvm.vector.reduce.and.v256i1(<256 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 520 for instruction: %V512 = call i1 @llvm.vector.reduce.and.v512i1(<512 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 1040 for instruction: %V1024 = call i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
Expand All @@ -33,6 +39,9 @@ define i32 @reduce_i1(i32 %arg) {
%V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
%V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
%V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
%V256 = call i1 @llvm.vector.reduce.and.v256i1(<256 x i1> undef)
%V512 = call i1 @llvm.vector.reduce.and.v512i1(<512 x i1> undef)
%V1024 = call i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1> undef)
ret i32 undef
}

Expand Down Expand Up @@ -136,6 +145,9 @@ declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
declare i1 @llvm.vector.reduce.and.v64i1(<64 x i1>)
declare i1 @llvm.vector.reduce.and.v128i1(<128 x i1>)
declare i1 @llvm.vector.reduce.and.v256i1(<256 x i1>)
declare i1 @llvm.vector.reduce.and.v512i1(<512 x i1>)
declare i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1>)
declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.and.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/Analysis/CostModel/RISCV/reduce-or.ll
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Expand Up @@ -12,6 +12,9 @@ define i32 @reduce_i1(i32 %arg) {
; RISCV32-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 132 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 264 for instruction: %V256 = call i1 @llvm.vector.reduce.or.v256i1(<256 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 528 for instruction: %V512 = call i1 @llvm.vector.reduce.or.v512i1(<512 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 1056 for instruction: %V1024 = call i1 @llvm.vector.reduce.or.v1024i1(<1024 x i1> undef)
; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
; RISCV64-LABEL: 'reduce_i1'
Expand All @@ -23,6 +26,9 @@ define i32 @reduce_i1(i32 %arg) {
; RISCV64-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %V256 = call i1 @llvm.vector.reduce.or.v256i1(<256 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 520 for instruction: %V512 = call i1 @llvm.vector.reduce.or.v512i1(<512 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 1040 for instruction: %V1024 = call i1 @llvm.vector.reduce.or.v1024i1(<1024 x i1> undef)
; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
Expand All @@ -33,6 +39,9 @@ define i32 @reduce_i1(i32 %arg) {
%V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
%V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
%V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
%V256 = call i1 @llvm.vector.reduce.or.v256i1(<256 x i1> undef)
%V512 = call i1 @llvm.vector.reduce.or.v512i1(<512 x i1> undef)
%V1024 = call i1 @llvm.vector.reduce.or.v1024i1(<1024 x i1> undef)
ret i32 undef
}

Expand Down Expand Up @@ -136,6 +145,9 @@ declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
declare i1 @llvm.vector.reduce.or.v128i1(<128 x i1>)
declare i1 @llvm.vector.reduce.or.v256i1(<256 x i1>)
declare i1 @llvm.vector.reduce.or.v512i1(<512 x i1>)
declare i1 @llvm.vector.reduce.or.v1024i1(<1024 x i1>)
declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.or.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
Expand Down

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