[AArch64][x86] add tests for bitwise logic + shifts; NFC

llvm · Feb 24, 2022 · ecf606c · ecf606c
1 parent 6159f05
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diff --git a/llvm/test/CodeGen/AArch64/logic-shift.ll b/llvm/test/CodeGen/AArch64/logic-shift.ll
@@ -0,0 +1,238 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+define i8 @or_lshr_commute0(i8 %x0, i8 %x1, i8 %y, i8 %z) {
+; CHECK-LABEL: or_lshr_commute0:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
+; CHECK-NEXT:    and w9, w1, #0xff
+; CHECK-NEXT:    lsr w8, w8, w2
+; CHECK-NEXT:    lsr w9, w9, w2
+; CHECK-NEXT:    orr w8, w8, w3
+; CHECK-NEXT:    orr w0, w8, w9
+; CHECK-NEXT:    ret
+  %sh1 = lshr i8 %x0, %y
+  %sh2 = lshr i8 %x1, %y
+  %logic = or i8 %sh1, %z
+  %r = or i8 %logic, %sh2
+  ret i8 %r
+}
+
+define i32 @or_lshr_commute1(i32 %x0, i32 %x1, i32 %y, i32 %z) {
+; CHECK-LABEL: or_lshr_commute1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr w8, w0, w2
+; CHECK-NEXT:    lsr w9, w1, w2
+; CHECK-NEXT:    orr w8, w3, w8
+; CHECK-NEXT:    orr w0, w8, w9
+; CHECK-NEXT:    ret
+  %sh1 = lshr i32 %x0, %y
+  %sh2 = lshr i32 %x1, %y
+  %logic = or i32 %z, %sh1
+  %r = or i32 %logic, %sh2
+  ret i32 %r
+}
+
+define <8 x i16> @or_lshr_commute2(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %y, <8 x i16> %z) {
+; CHECK-LABEL: or_lshr_commute2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    neg v2.8h, v2.8h
+; CHECK-NEXT:    ushl v0.8h, v0.8h, v2.8h
+; CHECK-NEXT:    ushl v1.8h, v1.8h, v2.8h
+; CHECK-NEXT:    orr v0.16b, v0.16b, v3.16b
+; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    ret
+  %sh1 = lshr <8 x i16> %x0, %y
+  %sh2 = lshr <8 x i16> %x1, %y
+  %logic = or <8 x i16> %sh1, %z
+  %r = or <8 x i16> %sh2, %logic
+  ret <8 x i16> %r
+}
+
+define <2 x i64> @or_lshr_commute3(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %y, <2 x i64> %z) {
+; CHECK-LABEL: or_lshr_commute3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    neg v2.2d, v2.2d
+; CHECK-NEXT:    ushl v0.2d, v0.2d, v2.2d
+; CHECK-NEXT:    ushl v1.2d, v1.2d, v2.2d
+; CHECK-NEXT:    orr v0.16b, v3.16b, v0.16b
+; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    ret
+  %sh1 = lshr <2 x i64> %x0, %y
+  %sh2 = lshr <2 x i64> %x1, %y
+  %logic = or <2 x i64> %z, %sh1
+  %r = or <2 x i64> %sh2, %logic
+  ret <2 x i64> %r
+}
+
+define i16 @or_ashr_commute0(i16 %x0, i16 %x1, i16 %y, i16 %z) {
+; CHECK-LABEL: or_ashr_commute0:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sxth w8, w0
+; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
+; CHECK-NEXT:    sxth w9, w1
+; CHECK-NEXT:    asr w8, w8, w2
+; CHECK-NEXT:    asr w9, w9, w2
+; CHECK-NEXT:    orr w8, w8, w3
+; CHECK-NEXT:    orr w0, w8, w9
+; CHECK-NEXT:    ret
+  %sh1 = ashr i16 %x0, %y
+  %sh2 = ashr i16 %x1, %y
+  %logic = or i16 %sh1, %z
+  %r = or i16 %logic, %sh2
+  ret i16 %r
+}
+
+define i64 @or_ashr_commute1(i64 %x0, i64 %x1, i64 %y, i64 %z) {
+; CHECK-LABEL: or_ashr_commute1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr x8, x0, x2
+; CHECK-NEXT:    asr x9, x1, x2
+; CHECK-NEXT:    orr x8, x3, x8
+; CHECK-NEXT:    orr x0, x8, x9
+; CHECK-NEXT:    ret
+  %sh1 = ashr i64 %x0, %y
+  %sh2 = ashr i64 %x1, %y
+  %logic = or i64 %z, %sh1
+  %r = or i64 %logic, %sh2
+  ret i64 %r
+}
+
+define <4 x i32> @or_ashr_commute2(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: or_ashr_commute2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    neg v2.4s, v2.4s
+; CHECK-NEXT:    sshl v0.4s, v0.4s, v2.4s
+; CHECK-NEXT:    sshl v1.4s, v1.4s, v2.4s
+; CHECK-NEXT:    orr v0.16b, v0.16b, v3.16b
+; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    ret
+  %sh1 = ashr <4 x i32> %x0, %y
+  %sh2 = ashr <4 x i32> %x1, %y
+  %logic = or <4 x i32> %sh1, %z
+  %r = or <4 x i32> %sh2, %logic
+  ret <4 x i32> %r
+}
+
+define <16 x i8> @or_ashr_commute3(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %y, <16 x i8> %z) {
+; CHECK-LABEL: or_ashr_commute3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    neg v2.16b, v2.16b
+; CHECK-NEXT:    sshl v0.16b, v0.16b, v2.16b
+; CHECK-NEXT:    sshl v1.16b, v1.16b, v2.16b
+; CHECK-NEXT:    orr v0.16b, v3.16b, v0.16b
+; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    ret
+  %sh1 = ashr <16 x i8> %x0, %y
+  %sh2 = ashr <16 x i8> %x1, %y
+  %logic = or <16 x i8> %z, %sh1
+  %r = or <16 x i8> %sh2, %logic
+  ret <16 x i8> %r
+}
+
+define i32 @or_shl_commute0(i32 %x0, i32 %x1, i32 %y, i32 %z) {
+; CHECK-LABEL: or_shl_commute0:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl w8, w0, w2
+; CHECK-NEXT:    lsl w9, w1, w2
+; CHECK-NEXT:    orr w8, w8, w3
+; CHECK-NEXT:    orr w0, w8, w9
+; CHECK-NEXT:    ret
+  %sh1 = shl i32 %x0, %y
+  %sh2 = shl i32 %x1, %y
+  %logic = or i32 %sh1, %z
+  %r = or i32 %logic, %sh2
+  ret i32 %r
+}
+
+define i8 @or_shl_commute1(i8 %x0, i8 %x1, i8 %y, i8 %z) {
+; CHECK-LABEL: or_shl_commute1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
+; CHECK-NEXT:    lsl w8, w0, w2
+; CHECK-NEXT:    lsl w9, w1, w2
+; CHECK-NEXT:    orr w8, w3, w8
+; CHECK-NEXT:    orr w0, w8, w9
+; CHECK-NEXT:    ret
+  %sh1 = shl i8 %x0, %y
+  %sh2 = shl i8 %x1, %y
+  %logic = or i8 %z, %sh1
+  %r = or i8 %logic, %sh2
+  ret i8 %r
+}
+
+define <2 x i64> @or_shl_commute2(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %y, <2 x i64> %z) {
+; CHECK-LABEL: or_shl_commute2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushl v0.2d, v0.2d, v2.2d
+; CHECK-NEXT:    ushl v1.2d, v1.2d, v2.2d
+; CHECK-NEXT:    orr v0.16b, v0.16b, v3.16b
+; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    ret
+  %sh1 = shl <2 x i64> %x0, %y
+  %sh2 = shl <2 x i64> %x1, %y
+  %logic = or <2 x i64> %sh1, %z
+  %r = or <2 x i64> %sh2, %logic
+  ret <2 x i64> %r
+}
+
+define <8 x i16> @or_shl_commute3(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %y, <8 x i16> %z) {
+; CHECK-LABEL: or_shl_commute3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushl v0.8h, v0.8h, v2.8h
+; CHECK-NEXT:    ushl v1.8h, v1.8h, v2.8h
+; CHECK-NEXT:    orr v0.16b, v3.16b, v0.16b
+; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    ret
+  %sh1 = shl <8 x i16> %x0, %y
+  %sh2 = shl <8 x i16> %x1, %y
+  %logic = or <8 x i16> %z, %sh1
+  %r = or <8 x i16> %sh2, %logic
+  ret <8 x i16> %r
+}
+
+define i64 @or_mix_shr(i64 %x0, i64 %x1, i64 %y, i64 %z) {
+; CHECK-LABEL: or_mix_shr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr x8, x0, x2
+; CHECK-NEXT:    lsr x9, x1, x2
+; CHECK-NEXT:    orr x8, x8, x3
+; CHECK-NEXT:    orr x0, x8, x9
+; CHECK-NEXT:    ret
+  %sh1 = ashr i64 %x0, %y
+  %sh2 = lshr i64 %x1, %y
+  %logic = or i64 %sh1, %z
+  %r = or i64 %logic, %sh2
+  ret i64 %r
+}
+
+define i64 @or_lshr_mix_shift_amount(i64 %x0, i64 %x1, i64 %y, i64 %z, i64 %w) {
+; CHECK-LABEL: or_lshr_mix_shift_amount:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr x9, x0, x2
+; CHECK-NEXT:    lsr x8, x1, x4
+; CHECK-NEXT:    orr x9, x9, x3
+; CHECK-NEXT:    orr x0, x9, x8
+; CHECK-NEXT:    ret
+  %sh1 = lshr i64 %x0, %y
+  %sh2 = lshr i64 %x1, %w
+  %logic = or i64 %sh1, %z
+  %r = or i64 %logic, %sh2
+  ret i64 %r
+}
+
+define i64 @mix_logic_lshr(i64 %x0, i64 %x1, i64 %y, i64 %z) {
+; CHECK-LABEL: mix_logic_lshr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr x8, x0, x2
+; CHECK-NEXT:    lsr x9, x1, x2
+; CHECK-NEXT:    eor x8, x8, x3
+; CHECK-NEXT:    orr x0, x8, x9
+; CHECK-NEXT:    ret
+  %sh1 = lshr i64 %x0, %y
+  %sh2 = lshr i64 %x1, %y
+  %logic = xor i64 %sh1, %z
+  %r = or i64 %logic, %sh2
+  ret i64 %r
+}