Skip to content

Commit

Permalink
[SelectionDAGBuilder] use bitcast instead of AnyExtOrTrunc if copy pa…
Browse files Browse the repository at this point in the history
…rts from an int vector to a float vector to fix issue #58615

The getCopyFromPartsVector doesn't work correctly when PartEVT and ValueVT have both different element type and different size.

This patch
1) removes the part of a comment that contains the incorrect assumption that element type are the same
2) use bitcast when copy parts of int vector to a float vector after the subvector extraction

Reviewed By: Peter, efriedma

Differential Revision: https://reviews.llvm.org/D136726
  • Loading branch information
HazyFish authored and DataCorrupted committed Nov 3, 2022
1 parent 3481898 commit ef0d689
Show file tree
Hide file tree
Showing 2 changed files with 16 additions and 4 deletions.
9 changes: 5 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Expand Up @@ -398,10 +398,9 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);

// If the element type of the source/dest vectors are the same, but the
// parts vector has more elements than the value vector, then we have a
// vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
// elements we want.
// If the parts vector has more elements than the value vector, then we
// have a vector widening case (e.g. <2 x float> -> <4 x float>).
// Extract the elements we want.
if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) {
assert((PartEVT.getVectorElementCount().getKnownMinValue() >
ValueVT.getVectorElementCount().getKnownMinValue()) &&
Expand All @@ -415,6 +414,8 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
DAG.getVectorIdxConstant(0, DL));
if (PartEVT == ValueVT)
return Val;
if (PartEVT.isInteger() && ValueVT.isFloatingPoint())
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
}

// Promoted vector extract
Expand Down
11 changes: 11 additions & 0 deletions llvm/test/CodeGen/AArch64/aarch64-v1f32-arg.ll
@@ -0,0 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s

define <1 x float> @f(<16 x i64> %0, <1 x float> %1) {
; CHECK-LABEL: f:
; CHECK: // %bb.0: // %BB
; CHECK-NEXT: ldr d0, [sp]
; CHECK-NEXT: ret
BB:
ret <1 x float> %1
}

0 comments on commit ef0d689

Please sign in to comment.