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[VE] Add isReMaterializable and isAsCheapAsAMove flags
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Add isReMaterializable and isCheapAsAMove flags to integer instructions
which cost cheap.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90833
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@kaz7
kaz7 committed Nov 5, 2020
1 parent f552474 commit f0e585d
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Showing 11 changed files with 125 additions and 101 deletions.
32 changes: 28 additions & 4 deletions llvm/lib/Target/VE/VEInstrInfo.td
View file
Expand Up @@ -938,10 +938,11 @@ multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC> {
}

// Section 8.2.1 - LEA
let cx = 0, DecoderMethod = "DecodeLoadI64" in
defm LEA : RMm<"lea", 0x06, I64>;
let cx = 1, DecoderMethod = "DecodeLoadI64" in
defm LEASL : RMm<"lea.sl", 0x06, I64>;
let isReMaterializable = 1, isAsCheapAsAMove = 1,
DecoderMethod = "DecodeLoadI64" in {
let cx = 0 in defm LEA : RMm<"lea", 0x06, I64>;
let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64>;
}

def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;
def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
Expand Down Expand Up @@ -1140,6 +1141,8 @@ def SVOB : RR<0x30, (outs), (ins), "svob">;
// Section 8.4 - Fixed-point Operation Instructions
//-----------------------------------------------------------------------------

let isReMaterializable = 1, isAsCheapAsAMove = 1 in {

// Section 8.4.1 - ADD (Add)
defm ADDUL : RRm<"addu.l", 0x48, I64, i64>;
let cx = 1 in defm ADDUW : RRm<"addu.w", 0x48, I32, i32>;
Expand All @@ -1162,6 +1165,8 @@ let cx = 1 in defm SUBSWZX : RRNCm<"subs.w.zx", 0x5A, I32, i32>;
// Section 8.4.6 - SBX (Subtract)
defm SUBSL : RRNCm<"subs.l", 0x5B, I64, i64, sub>;

} // isReMaterializable, isAsCheapAsAMove

// Section 8.4.7 - MPY (Multiply)
defm MULUL : RRm<"mulu.l", 0x49, I64, i64>;
let cx = 1 in defm MULUW : RRm<"mulu.w", 0x49, I32, i32>;
Expand All @@ -1187,6 +1192,8 @@ let cx = 1 in defm DIVSWZX : RRNCm<"divs.w.zx", 0x7B, I32, i32>;
// Section 8.4.13 - DVX (Divide)
defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>;

let isReMaterializable = 1, isAsCheapAsAMove = 1 in {

// Section 8.4.14 - CMP (Compare)
defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64>;
let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32>;
Expand All @@ -1209,10 +1216,14 @@ let cx = 1, cw = 1 in defm MINSWZX : RRm<"mins.w.zx", 0x78, I32, i32>;
defm MAXSL : RRm<"maxs.l", 0x68, I64, i64>;
let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>;

} // isReMaterializable, isAsCheapAsAMove

//-----------------------------------------------------------------------------
// Section 8.5 - Logical Operation Instructions
//-----------------------------------------------------------------------------

let isReMaterializable = 1, isAsCheapAsAMove = 1 in {

// Section 8.5.1 - AND (AND)
defm AND : RRm<"and", 0x44, I64, i64, and>;

Expand All @@ -1225,9 +1236,12 @@ defm XOR : RRm<"xor", 0x46, I64, i64, xor>;
// Section 8.5.4 - EQV (Equivalence)
defm EQV : RRm<"eqv", 0x47, I64, i64>;

} // isReMaterializable, isAsCheapAsAMove

// Section 8.5.5 - NND (Negate AND)
def and_not : PatFrags<(ops node:$x, node:$y),
[(and (not node:$x), node:$y)]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
defm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>;

// Section 8.5.6 - MRG (Merge)
Expand All @@ -1237,16 +1251,20 @@ defm MRG : RRMRGm<"mrg", 0x56, I64, i64>;
def ctlz_pat : PatFrags<(ops node:$src),
[(ctlz node:$src),
(ctlz_zero_undef node:$src)]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
defm LDZ : RRI1m<"ldz", 0x67, I64, i64, ctlz_pat>;

// Section 8.5.8 - PCNT (Population Count)
defm PCNT : RRI1m<"pcnt", 0x38, I64, i64, ctpop>;

// Section 8.5.9 - BRV (Bit Reverse)
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
defm BRV : RRI1m<"brv", 0x39, I64, i64, bitreverse>;

// Section 8.5.10 - BSWP (Byte Swap)
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
defm BSWP : RRSWPm<"bswp", 0x2B, I64, i64>;

def : Pat<(i64 (bswap i64:$src)),
(BSWPri $src, 0)>;
def : Pat<(i64 (bswap (i64 mimm:$src))),
Expand All @@ -1273,17 +1291,21 @@ def : MnemonicAlias<"cmov.s", "cmov.s.at">;
//-----------------------------------------------------------------------------

// Section 8.6.1 - SLL (Shift Left Logical)
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;

// Section 8.6.2 - SLD (Shift Left Double)
defm SLD : RRILDm<"sld", 0x64, I64, i64>;

// Section 8.6.3 - SRL (Shift Right Logical)
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;

// Section 8.6.4 - SRD (Shift Right Double)
defm SRD : RRIRDm<"srd", 0x74, I64, i64>;

let isReMaterializable = 1, isAsCheapAsAMove = 1 in {

// Section 8.6.5 - SLA (Shift Left Arithmetic)
defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
Expand All @@ -1298,6 +1320,8 @@ let cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>;
// Section 8.6.8 - SRAX (Shift Right Arithmetic)
defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>;

} // isReMaterializable, isAsCheapAsAMove

def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))),
(EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
$src, sub_i32), !add(32, 64)), imm:$val), sub_i32)>;
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/VE/Scalar/br_cc.ll
View file
Expand Up @@ -523,7 +523,7 @@ define void @br_cc_i128_imm(i128 %0) {
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s2
; CHECK-NEXT: or %s3, 0, %s2
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: or %s4, 63, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s4
Expand Down Expand Up @@ -553,7 +553,7 @@ define void @br_cc_u128_imm(i128 %0) {
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s2
; CHECK-NEXT: or %s3, 0, %s2
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1
; CHECK-NEXT: or %s4, 63, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s4
Expand Down Expand Up @@ -856,15 +856,15 @@ define void @br_cc_imm_i128(i128 %0) {
; CHECK-LABEL: br_cc_imm_i128:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: or %s2, -1, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s2
; CHECK-NEXT: or %s2, 0, %s3
; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s1
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s1
; CHECK-NEXT: or %s4, -64, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s4
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s2, %s3, %s1
; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
Expand All @@ -887,15 +887,15 @@ define void @br_cc_imm_u128(i128 %0) {
; CHECK-LABEL: br_cc_imm_u128:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: or %s2, -1, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s2
; CHECK-NEXT: or %s2, 0, %s3
; CHECK-NEXT: cmov.l.ne %s2, (63)0, %s1
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1
; CHECK-NEXT: or %s4, -64, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s4
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s2, %s3, %s1
; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/VE/Scalar/call.ll
View file
Expand Up @@ -50,9 +50,10 @@ define i32 @stack_call_int_szext() {
; CHECK-NEXT: or %s0, -1, (0)1
; CHECK-NEXT: st %s0, 248(, %s11)
; CHECK-NEXT: lea %s34, 65535
; CHECK-NEXT: lea %s1, stack_callee_int_szext@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s12, stack_callee_int_szext@hi(, %s1)
; CHECK-NEXT: lea %s0, stack_callee_int_szext@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, stack_callee_int_szext@hi(, %s0)
; CHECK-NEXT: or %s0, -1, (0)1
; CHECK-NEXT: lea %s1, 255
; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 4, (0)1
Expand All @@ -73,6 +74,9 @@ define float @stack_call_float() {
; CHECK-NEXT: lea.sl %s0, 1092616192
; CHECK-NEXT: st %s0, 248(, %s11)
; CHECK-NEXT: lea.sl %s34, 1091567616
; CHECK-NEXT: lea %s0, stack_callee_float@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, stack_callee_float@hi(, %s0)
; CHECK-NEXT: lea.sl %s0, 1065353216
; CHECK-NEXT: lea.sl %s1, 1073741824
; CHECK-NEXT: lea.sl %s2, 1077936128
Expand All @@ -81,9 +85,6 @@ define float @stack_call_float() {
; CHECK-NEXT: lea.sl %s5, 1086324736
; CHECK-NEXT: lea.sl %s6, 1088421888
; CHECK-NEXT: lea.sl %s7, 1090519040
; CHECK-NEXT: lea %s35, stack_callee_float@lo
; CHECK-NEXT: and %s35, %s35, (32)0
; CHECK-NEXT: lea.sl %s12, stack_callee_float@hi(, %s35)
; CHECK-NEXT: st %s34, 240(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
Expand Down Expand Up @@ -111,4 +112,3 @@ define float @stack_call_float2(float %p0) {
%r = tail call float @stack_callee_float(float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0)
ret float %r
}

12 changes: 6 additions & 6 deletions llvm/test/CodeGen/VE/Scalar/ctlz.ll
View file
Expand Up @@ -10,12 +10,12 @@ define i128 @func128(i128 %p){
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s3, %s1, %s2
; CHECK-NEXT: cmps.l %s2, %s1, %s2
; CHECK-NEXT: ldz %s1, %s1
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s3
; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true)
ret i128 %r
Expand Down Expand Up @@ -180,12 +180,12 @@ define i128 @func128x(i128 %p){
; CHECK-LABEL: func128x:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s3, %s1, %s2
; CHECK-NEXT: cmps.l %s2, %s1, %s2
; CHECK-NEXT: ldz %s1, %s1
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s3
; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false)
ret i128 %r
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/VE/Scalar/cttz.ll
View file
Expand Up @@ -10,16 +10,16 @@ define i128 @func128(i128 %p) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s3, %s0, %s2
; CHECK-NEXT: lea %s4, -1(, %s0)
; CHECK-NEXT: nnd %s0, %s0, %s4
; CHECK-NEXT: pcnt %s4, %s0
; CHECK-NEXT: cmps.l %s2, %s0, %s2
; CHECK-NEXT: lea %s3, -1(, %s0)
; CHECK-NEXT: nnd %s0, %s0, %s3
; CHECK-NEXT: pcnt %s3, %s0
; CHECK-NEXT: lea %s0, -1(, %s1)
; CHECK-NEXT: nnd %s0, %s1, %s0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s4, %s3
; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: cmov.l.ne %s0, %s3, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true)
ret i128 %r
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/VE/Scalar/fp_frem.ll
View file
Expand Up @@ -75,10 +75,10 @@ define float @frem_float_zero(float %0) {
; CHECK-LABEL: frem_float_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, fmodf@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, fmodf@hi(, %s0)
; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: lea %s2, fmodf@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, fmodf@hi(, %s2)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%2 = frem float 0.000000e+00, %0
Expand Down Expand Up @@ -125,10 +125,10 @@ define float @frem_float_cont(float %0) {
; CHECK-LABEL: frem_float_cont:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, fmodf@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, fmodf@hi(, %s0)
; CHECK-NEXT: lea.sl %s0, -1073741824
; CHECK-NEXT: lea %s2, fmodf@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, fmodf@hi(, %s2)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%2 = frem float -2.000000e+00, %0
Expand Down
13 changes: 6 additions & 7 deletions llvm/test/CodeGen/VE/Scalar/selectccf32c.ll
View file
Expand Up @@ -59,15 +59,15 @@ define float @selectccsgti64(i64, i64, float, float) {
define float @selectccsgti128(i128, i128, float, float) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
; CHECK-NEXT: or %s2, 0, %s6
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s3, %s6
; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
Expand Down Expand Up @@ -99,4 +99,3 @@ define float @selectccogtf64(double, double, float, float) {
%6 = select i1 %5, float %2, float %3
ret float %6
}

13 changes: 6 additions & 7 deletions llvm/test/CodeGen/VE/Scalar/selectccf64c.ll
View file
Expand Up @@ -59,15 +59,15 @@ define double @selectccsgti64(i64, i64, double, double) {
define double @selectccsgti128(i128, i128, double, double) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
; CHECK-NEXT: or %s2, 0, %s6
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s3, %s6
; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
Expand Down Expand Up @@ -99,4 +99,3 @@ define double @selectccogtf64(double, double, double, double) {
%6 = select i1 %5, double %2, double %3
ret double %6
}

13 changes: 6 additions & 7 deletions llvm/test/CodeGen/VE/Scalar/selectcci32c.ll
View file
Expand Up @@ -59,15 +59,15 @@ define i32 @selectccsgti64(i64, i64, i32, i32) {
define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
; CHECK-NEXT: or %s2, 0, %s6
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s3, %s6
; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
Expand Down Expand Up @@ -99,4 +99,3 @@ define i32 @selectccogtf64(double, double, i32, i32) {
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
}

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