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[SVE2.1][Clang][LLVM]Int/FP reduce builtin in Clang and LLVM intrinsic (
#69926) This patch implements the builtins in Clang and the LLVM-IR intrinsic for the following: // Variants are also available for: // _s8, _s16, _u16, _s32, _u32, _s64, _u64, // _f16, _f32, _f64uint8x16_t svaddqv[_u8](svbool_t pg, svuint8_t zn); // Variants are also available for: // _s8, _u16, _s16, _u32, _s32, _u64, _s64 uint8x16_t svandqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t sveorqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t svorqv[_u8](svbool_t pg, svuint8_t zn); // Variants are also available for: // _s8, _u16, _s16, _u32, _s32, _u64, _s64; uint8x16_t svmaxqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t svminqv[_u8](svbool_t pg, svuint8_t zn); // Variants are also available for _f32, _f64 float16x8_t svmaxnmqv[_f16](svbool_t pg, svfloat16_t zn); float16x8_t svminnmqv[_f16](svbool_t pg, svfloat16_t zn); According to the PR#257[1] The reduction instruction uses scalable vectors as input and fixed vectors as output, therefore we changed SVEEmitter to emit fixed vector types in case the neon header(arm_neon.h) is not present. [1]ARM-software/acle#257 Co-author: Dinar Temirbulatov <dinar.temirbulatov@arm.com>
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clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py | ||
// REQUIRES: aarch64-registered-target | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK | ||
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s | ||
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK | ||
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
#include <arm_neon.h> | ||
#include <arm_sve.h> | ||
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#ifdef SVE_OVERLOADED_FORMS | ||
// A simple used,unused... macro, long enough to represent any SVE builtin. | ||
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 | ||
#else | ||
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 | ||
#endif | ||
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// FADDQV | ||
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// CHECK-LABEL: @test_svaddqv_f16( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svaddqv_f16u10__SVBool_tu13__SVFloat16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
float16x8_t test_svaddqv_f16(svbool_t pg, svfloat16_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svaddqv,,_f16,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svaddqv_f32( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svaddqv_f32u10__SVBool_tu13__SVFloat32_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
float32x4_t test_svaddqv_f32(svbool_t pg, svfloat32_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svaddqv,,_f32,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svaddqv_f64( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svaddqv_f64u10__SVBool_tu13__SVFloat64_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
float64x2_t test_svaddqv_f64(svbool_t pg, svfloat64_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svaddqv,,_f64,)(pg, op); | ||
} | ||
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// FMAXQV | ||
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// CHECK-LABEL: @test_svmaxqv_f16( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f16u10__SVBool_tu13__SVFloat16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
float16x8_t test_svmaxqv_f16(svbool_t pg, svfloat16_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svmaxqv,,_f16,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svmaxqv_f32( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f32u10__SVBool_tu13__SVFloat32_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
float32x4_t test_svmaxqv_f32(svbool_t pg, svfloat32_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svmaxqv,,_f32,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svmaxqv_f64( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f64u10__SVBool_tu13__SVFloat64_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
float64x2_t test_svmaxqv_f64(svbool_t pg, svfloat64_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svmaxqv,,_f64,)(pg, op); | ||
} | ||
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// FMINQV | ||
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// CHECK-LABEL: @test_svminqv_f16( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svminqv_f16u10__SVBool_tu13__SVFloat16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
float16x8_t test_svminqv_f16(svbool_t pg, svfloat16_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svminqv,,_f16,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svminqv_f32( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svminqv_f32u10__SVBool_tu13__SVFloat32_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
float32x4_t test_svminqv_f32(svbool_t pg, svfloat32_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svminqv,,_f32,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svminqv_f64( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z16test_svminqv_f64u10__SVBool_tu13__SVFloat64_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
float64x2_t test_svminqv_f64(svbool_t pg, svfloat64_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svminqv,,_f64,)(pg, op); | ||
} | ||
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// FMAXNMQV | ||
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// CHECK-LABEL: @test_svmaxnmqv_f16( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f16u10__SVBool_tu13__SVFloat16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
float16x8_t test_svmaxnmqv_f16(svbool_t pg, svfloat16_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svmaxnmqv,,_f16,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svmaxnmqv_f32( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f32u10__SVBool_tu13__SVFloat32_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
float32x4_t test_svmaxnmqv_f32(svbool_t pg, svfloat32_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svmaxnmqv,,_f32,)(pg, op); | ||
} | ||
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// CHECK-LABEL: @test_svmaxnmqv_f64( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f64u10__SVBool_tu13__SVFloat64_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
float64x2_t test_svmaxnmqv_f64(svbool_t pg, svfloat64_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svmaxnmqv,,_f64,)(pg, op); | ||
} | ||
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// FMINNMQV | ||
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// CHECK-LABEL: @test_svminnmqv_f16( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f16u10__SVBool_tu13__SVFloat16_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] | ||
// | ||
float16x8_t test_svminnmqv_f16(svbool_t pg, svfloat16_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svminnmqv,,_f16,)(pg, op); | ||
} | ||
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||
// CHECK-LABEL: @test_svminnmqv_f32( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f32u10__SVBool_tu13__SVFloat32_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] | ||
// | ||
float32x4_t test_svminnmqv_f32(svbool_t pg, svfloat32_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svminnmqv,,_f32,)(pg, op); | ||
} | ||
|
||
// CHECK-LABEL: @test_svminnmqv_f64( | ||
// CHECK-NEXT: entry: | ||
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f64u10__SVBool_tu13__SVFloat64_t( | ||
// CPP-CHECK-NEXT: entry: | ||
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) | ||
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) | ||
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] | ||
// | ||
float64x2_t test_svminnmqv_f64(svbool_t pg, svfloat64_t op) | ||
{ | ||
return SVE_ACLE_FUNC(svminnmqv,,_f64,)(pg, op); | ||
} |
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