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Unify the target opcode enum in TargetOpcodes.h and the FixedInstrs a…
…rray in CodeGenTarget.cpp to avoid the ordering dependence. NFCI. Differential Revision: http://reviews.llvm.org/D16826 llvm-svn: 259726
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David L Kreitzer
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Feb 3, 2016
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//===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===// | ||
// | ||
// The LLVM Compiler Infrastructure | ||
// | ||
// This file is distributed under the University of Illinois Open Source | ||
// License. See LICENSE.TXT for details. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This file defines the target independent instruction opcodes. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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// NOTE: NO INCLUDE GUARD DESIRED! | ||
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/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. | ||
/// | ||
#ifndef HANDLE_TARGET_OPCODE | ||
#define HANDLE_TARGET_OPCODE(OPC, NUM) | ||
#endif | ||
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/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. | ||
/// | ||
#ifndef HANDLE_TARGET_OPCODE_MARKER | ||
#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) | ||
#endif | ||
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/// Every instruction defined here must also appear in Target.td. | ||
/// | ||
HANDLE_TARGET_OPCODE(PHI, 0) | ||
HANDLE_TARGET_OPCODE(INLINEASM, 1) | ||
HANDLE_TARGET_OPCODE(CFI_INSTRUCTION, 2) | ||
HANDLE_TARGET_OPCODE(EH_LABEL, 3) | ||
HANDLE_TARGET_OPCODE(GC_LABEL, 4) | ||
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/// KILL - This instruction is a noop that is used only to adjust the | ||
/// liveness of registers. This can be useful when dealing with | ||
/// sub-registers. | ||
HANDLE_TARGET_OPCODE(KILL, 5) | ||
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/// EXTRACT_SUBREG - This instruction takes two operands: a register | ||
/// that has subregisters, and a subregister index. It returns the | ||
/// extracted subregister value. This is commonly used to implement | ||
/// truncation operations on target architectures which support it. | ||
HANDLE_TARGET_OPCODE(EXTRACT_SUBREG, 6) | ||
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/// INSERT_SUBREG - This instruction takes three operands: a register that | ||
/// has subregisters, a register providing an insert value, and a | ||
/// subregister index. It returns the value of the first register with the | ||
/// value of the second register inserted. The first register is often | ||
/// defined by an IMPLICIT_DEF, because it is commonly used to implement | ||
/// anyext operations on target architectures which support it. | ||
HANDLE_TARGET_OPCODE(INSERT_SUBREG, 7) | ||
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. | ||
HANDLE_TARGET_OPCODE(IMPLICIT_DEF, 8) | ||
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that | ||
/// the first operand is an immediate integer constant. This constant is | ||
/// often zero, because it is commonly used to assert that the instruction | ||
/// defining the register implicitly clears the high bits. | ||
HANDLE_TARGET_OPCODE(SUBREG_TO_REG, 9) | ||
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain | ||
/// register-to-register copy into a specific register class. This is only | ||
/// used between instruction selection and MachineInstr creation, before | ||
/// virtual registers have been created for all the instructions, and it's | ||
/// only needed in cases where the register classes implied by the | ||
/// instructions are insufficient. It is emitted as a COPY MachineInstr. | ||
HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS, 10) | ||
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic | ||
HANDLE_TARGET_OPCODE(DBG_VALUE, 11) | ||
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/// REG_SEQUENCE - This variadic instruction is used to form a register that | ||
/// represents a consecutive sequence of sub-registers. It's used as a | ||
/// register coalescing / allocation aid and must be eliminated before code | ||
/// emission. | ||
// In SDNode form, the first operand encodes the register class created by | ||
// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index | ||
// pair. Once it has been lowered to a MachineInstr, the regclass operand | ||
// is no longer present. | ||
/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 | ||
/// After register coalescing references of v1024 should be replace with | ||
/// v1027:3, v1025 with v1027:4, etc. | ||
HANDLE_TARGET_OPCODE(REG_SEQUENCE, 12) | ||
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/// COPY - Target-independent register copy. This instruction can also be | ||
/// used to copy between subregisters of virtual registers. | ||
HANDLE_TARGET_OPCODE(COPY, 13) | ||
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/// BUNDLE - This instruction represents an instruction bundle. Instructions | ||
/// which immediately follow a BUNDLE instruction which are marked with | ||
/// 'InsideBundle' flag are inside the bundle. | ||
HANDLE_TARGET_OPCODE(BUNDLE, 14) | ||
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/// Lifetime markers. | ||
HANDLE_TARGET_OPCODE(LIFETIME_START, 15) | ||
HANDLE_TARGET_OPCODE(LIFETIME_END, 16) | ||
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/// A Stackmap instruction captures the location of live variables at its | ||
/// position in the instruction stream. It is followed by a shadow of bytes | ||
/// that must lie within the function and not contain another stackmap. | ||
HANDLE_TARGET_OPCODE(STACKMAP, 17) | ||
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/// Patchable call instruction - this instruction represents a call to a | ||
/// constant address, followed by a series of NOPs. It is intended to | ||
/// support optimizations for dynamic languages (such as javascript) that | ||
/// rewrite calls to runtimes with more efficient code sequences. | ||
/// This also implies a stack map. | ||
HANDLE_TARGET_OPCODE(PATCHPOINT, 18) | ||
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/// This pseudo-instruction loads the stack guard value. Targets which need | ||
/// to prevent the stack guard value or address from being spilled to the | ||
/// stack should override TargetLowering::emitLoadStackGuardNode and | ||
/// additionally expand this pseudo after register allocation. | ||
HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD, 19) | ||
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/// Call instruction with associated vm state for deoptimization and list | ||
/// of live pointers for relocation by the garbage collector. It is | ||
/// intended to support garbage collection with fully precise relocating | ||
/// collectors and deoptimizations in either the callee or caller. | ||
HANDLE_TARGET_OPCODE(STATEPOINT, 20) | ||
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/// Instruction that records the offset of a local stack allocation passed to | ||
/// llvm.localescape. It has two arguments: the symbol for the label and the | ||
/// frame index of the local stack allocation. | ||
HANDLE_TARGET_OPCODE(LOCAL_ESCAPE, 21) | ||
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/// Loading instruction that may page fault, bundled with associated | ||
/// information on how to handle such a page fault. It is intended to support | ||
/// "zero cost" null checks in managed languages by allowing LLVM to fold | ||
/// comparisons into existing memory operations. | ||
HANDLE_TARGET_OPCODE(FAULTING_LOAD_OP, 22) | ||
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/// The following generic opcodes are not supposed to appear after ISel. | ||
/// This is something we might want to relax, but for now, this is convenient | ||
/// to produce diagnostics. | ||
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/// Generic ADD instruction. This is an integer add. | ||
HANDLE_TARGET_OPCODE(G_ADD, 23) | ||
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) | ||
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// TODO: Add more generic opcodes as we move along. | ||
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/// Marker for the end of the generic opcode. | ||
/// This is used to check if an opcode is in the range of the | ||
/// generic opcodes. | ||
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_ADD) | ||
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/// BUILTIN_OP_END - This must be the last enum value in this list. | ||
/// The target-specific post-isel opcode values start here. | ||
HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) |
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