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[7/11][POC][Clang][RISCV] Define tuple type variant of vssseg2e32
For the cover letter of this patch-set, please checkout D146872. Depends on D147912. This is the 7th patch of the patch-set. This patch is a proof-of-concept and will be extended to full coverage in the future. Currently, the old non-tuple strided segment store is not removed, and only signed integer strided segment store of NF=2, EEW=32 is defined here. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D147913
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...t/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32_tuple.c
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 | ||
// REQUIRES: riscv-registered-target | ||
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ | ||
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ | ||
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ | ||
// RUN: FileCheck --check-prefix=CHECK-RV64 %s | ||
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#include <riscv_vector.h> | ||
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// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e32_v_tuple_i32m1 | ||
// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE0:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
// CHECK-RV64-NEXT: entry: | ||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[V_TUPLE_COERCE0]], 0 | ||
// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[V_TUPLE_COERCE1]], 1 | ||
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 0 | ||
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 1 | ||
// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv2i32.i64(<vscale x 2 x i32> [[TMP2]], <vscale x 2 x i32> [[TMP3]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]]) | ||
// CHECK-RV64-NEXT: ret void | ||
// | ||
void test_vssseg2e32_v_tuple_i32m1(int32_t *base, ptrdiff_t bstride, vint32m1x2_t v_tuple, size_t vl) { | ||
return __riscv_vssseg2e32_v_tuple_i32m1(base, bstride, v_tuple, vl); | ||
} | ||
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// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e32_v_tuple_i32m1_m | ||
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE0:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
// CHECK-RV64-NEXT: entry: | ||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[V_TUPLE_COERCE0]], 0 | ||
// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[V_TUPLE_COERCE1]], 1 | ||
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 0 | ||
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 1 | ||
// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP2]], <vscale x 2 x i32> [[TMP3]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]]) | ||
// CHECK-RV64-NEXT: ret void | ||
// | ||
void test_vssseg2e32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, ptrdiff_t bstride, vint32m1x2_t v_tuple, size_t vl) { | ||
return __riscv_vssseg2e32_v_tuple_i32m1_m(mask, base, bstride, v_tuple, vl); | ||
} |