[AArch64] fjcvtzs,rmif,cfinv,setf* all clobber nzcv

Differential Revision: https://reviews.llvm.org/D83818
llvm · Jul 27, 2020 · f5e1ec8 · f5e1ec8
1 parent 4dd5c2b
commit f5e1ec8
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Showing 11 changed files with 150 additions and 2 deletions.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1942,6 +1942,7 @@ class BaseFlagManipulation<bit sf, bit sz, dag iops, string asm, string ops>
     : I<(outs), iops, asm, ops, "", []>,
       Sched<[WriteI, ReadI, ReadI]> {
   let Uses = [NZCV];
+  let Defs = [NZCV];
   bits<5> Rn;
   let Inst{31}    = sf;
   let Inst{30-15} = 0b0111010000000000;

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1030,7 +1030,7 @@ let Predicates = [HasPA] in {
 }
 
 // v8.3a floating point conversion for javascript
-let Predicates = [HasJS, HasFPARMv8] in
+let Predicates = [HasJS, HasFPARMv8], Defs = [NZCV] in
 def FJCVTZS  : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
                                       "fjcvtzs",
                                       [(set GPR32:$Rd,
@@ -1039,7 +1039,7 @@ def FJCVTZS  : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
 } // HasJS, HasFPARMv8
 
 // v8.4 Flag manipulation instructions
-let Predicates = [HasFMI] in {
+let Predicates = [HasFMI], Defs = [NZCV], Uses = [NZCV] in {
 def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
   let Inst{20-5} = 0b0000001000000000;
 }

diff --git a/llvm/test/CodeGen/AArch64/cfinv-def-nzcv.mir b/llvm/test/CodeGen/AArch64/cfinv-def-nzcv.mir
@@ -0,0 +1,17 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+11]]:29: missing implicit register operand 'implicit $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$w0' }
+  - { reg: '$x0' }
+body:             |
+  bb.0:
+    liveins: $w0, $x0
+
+    CFINV implicit-def $nzcv
+    RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/cfinv-use-nzcv.mir b/llvm/test/CodeGen/AArch64/cfinv-use-nzcv.mir
@@ -0,0 +1,17 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+11]]:25: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$w0' }
+  - { reg: '$x0' }
+body:             |
+  bb.0:
+    liveins: $w0, $x0
+
+    CFINV implicit $nzcv
+    RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/fjcvtzs.mir b/llvm/test/CodeGen/AArch64/fjcvtzs.mir
@@ -0,0 +1,17 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -mattr=+jsconv -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+11]]:49: missing implicit register operand 'implicit-def $nzcv'
+
+...
+---
+name:            test_jcvt
+liveins:
+  - { reg: '$d0' }
+body:             |
+  bb.0:
+    liveins: $d0
+
+    renamable $w0 = FJCVTZS killed renamable $d0
+    RET undef $lr, implicit killed $w0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/rmif-def-nzcv.mir b/llvm/test/CodeGen/AArch64/rmif-def-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:49: missing implicit register operand 'implicit $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$x0' }
+body:             |
+  bb.0:
+    liveins: $x0
+
+    RMIF renamable $x0, 0, 0, implicit-def $nzcv
+    RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/rmif-use-nzcv.mir b/llvm/test/CodeGen/AArch64/rmif-use-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:45: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$x0' }
+body:             |
+  bb.0:
+    liveins: $x0
+
+    RMIF renamable $x0, 0, 0, implicit $nzcv
+    RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf16-def-nzcv.mir b/llvm/test/CodeGen/AArch64/setf16-def-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:45: missing implicit register operand 'implicit $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$w0' }
+body:             |
+  bb.0:
+    liveins: $w0
+
+    SETF16 renamable $w0, implicit-def $nzcv
+    RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf16-use-nzcv.mir b/llvm/test/CodeGen/AArch64/setf16-use-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:41: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$w0' }
+body:             |
+  bb.0:
+    liveins: $w0
+
+    SETF16 renamable $w0, implicit $nzcv
+    RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf8-def-nzcv.mir b/llvm/test/CodeGen/AArch64/setf8-def-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:44: missing implicit register operand 'implicit $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$w0' }
+body:             |
+  bb.0:
+    liveins: $w0
+
+    SETF8 renamable $w0, implicit-def $nzcv
+    RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf8-use-nzcv.mir b/llvm/test/CodeGen/AArch64/setf8-use-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:40: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$w0' }
+body:             |
+  bb.0:
+    liveins: $w0
+
+    SETF8 renamable $w0, implicit $nzcv
+    RET undef $lr, implicit killed $w0
+
+