Skip to content

Commit

Permalink
[RISCV][NFC] Add common check prefix to reduce duplicate check lines.
Browse files Browse the repository at this point in the history 
Differential Revision: https://reviews.llvm.org/D122120
  • Loading branch information
jacquesguan authored and jacquesguan committed Mar 22, 2022
1 parent 9f90254 commit f863df9
Show file tree
Hide file tree
Showing 12 changed files with 1,109 additions and 2,401 deletions.
38 changes: 13 additions & 25 deletions llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
View file
Original file line number Diff line number Diff line change
@@ -1,32 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s --check-prefix=RV64
; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV64

; Check that we correctly scale the split part indirect offsets by VSCALE.
define <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y) {
; RV32-LABEL: callee_scalable_vector_split_indirect:
; RV32: # %bb.0:
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, a0, a1
; RV32-NEXT: vl8re32.v v24, (a0)
; RV32-NEXT: vl8re32.v v0, (a1)
; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: vadd.vv v16, v16, v0
; RV32-NEXT: ret
;
; RV64-LABEL: callee_scalable_vector_split_indirect:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, a0, a1
; RV64-NEXT: vl8re32.v v24, (a0)
; RV64-NEXT: vl8re32.v v0, (a1)
; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV64-NEXT: vadd.vv v8, v8, v24
; RV64-NEXT: vadd.vv v16, v16, v0
; RV64-NEXT: ret
; CHECK-LABEL: callee_scalable_vector_split_indirect:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vl8re32.v v0, (a1)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vv v8, v8, v24
; CHECK-NEXT: vadd.vv v16, v16, v0
; CHECK-NEXT: ret
%a = add <vscale x 32 x i32> %x, %y
ret <vscale x 32 x i32> %a
}
Expand Down
30 changes: 10 additions & 20 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64

declare <1 x i8> @llvm.masked.gather.v1i8.v1p0i8(<1 x i8*>, i32, <1 x i1>, <1 x i8>)

Expand Down Expand Up @@ -973,15 +973,10 @@ define <4 x i64> @mgather_truemask_v4i64(<4 x i64*> %ptrs, <4 x i64> %passthru)
}

define <4 x i64> @mgather_falsemask_v4i64(<4 x i64*> %ptrs, <4 x i64> %passthru) {
; RV32-LABEL: mgather_falsemask_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_falsemask_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
; CHECK-LABEL: mgather_falsemask_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> %ptrs, i32 8, <4 x i1> zeroinitializer, <4 x i64> %passthru)
ret <4 x i64> %v
}
Expand Down Expand Up @@ -1843,15 +1838,10 @@ define <4 x double> @mgather_truemask_v4f64(<4 x double*> %ptrs, <4 x double> %p
}

define <4 x double> @mgather_falsemask_v4f64(<4 x double*> %ptrs, <4 x double> %passthru) {
; RV32-LABEL: mgather_falsemask_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_falsemask_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
; CHECK-LABEL: mgather_falsemask_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%v = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> %ptrs, i32 8, <4 x i1> zeroinitializer, <4 x double> %passthru)
ret <4 x double> %v
}
Expand Down
74 changes: 23 additions & 51 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
; RUN: -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64

declare void @llvm.masked.scatter.v1i8.v1p0i8(<1 x i8>, <1 x i8*>, i32, <1 x i1>)

Expand Down Expand Up @@ -146,13 +146,9 @@ define void @mscatter_truemask_v4i8(<4 x i8> %val, <4 x i8*> %ptrs) {
}

define void @mscatter_falsemask_v4i8(<4 x i8> %val, <4 x i8*> %ptrs) {
; RV32-LABEL: mscatter_falsemask_v4i8:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_falsemask_v4i8:
; RV64: # %bb.0:
; RV64-NEXT: ret
; CHECK-LABEL: mscatter_falsemask_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: ret
call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %val, <4 x i8*> %ptrs, i32 1, <4 x i1> zeroinitializer)
ret void
}
Expand Down Expand Up @@ -311,13 +307,9 @@ define void @mscatter_truemask_v4i16(<4 x i16> %val, <4 x i16*> %ptrs) {
}

define void @mscatter_falsemask_v4i16(<4 x i16> %val, <4 x i16*> %ptrs) {
; RV32-LABEL: mscatter_falsemask_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_falsemask_v4i16:
; RV64: # %bb.0:
; RV64-NEXT: ret
; CHECK-LABEL: mscatter_falsemask_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: ret
call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> %val, <4 x i16*> %ptrs, i32 2, <4 x i1> zeroinitializer)
ret void
}
Expand Down Expand Up @@ -526,13 +518,9 @@ define void @mscatter_truemask_v4i32(<4 x i32> %val, <4 x i32*> %ptrs) {
}

define void @mscatter_falsemask_v4i32(<4 x i32> %val, <4 x i32*> %ptrs) {
; RV32-LABEL: mscatter_falsemask_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_falsemask_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: ret
; CHECK-LABEL: mscatter_falsemask_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: ret
call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %val, <4 x i32*> %ptrs, i32 4, <4 x i1> zeroinitializer)
ret void
}
Expand Down Expand Up @@ -785,13 +773,9 @@ define void @mscatter_truemask_v4i64(<4 x i64> %val, <4 x i64*> %ptrs) {
}

define void @mscatter_falsemask_v4i64(<4 x i64> %val, <4 x i64*> %ptrs) {
; RV32-LABEL: mscatter_falsemask_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_falsemask_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: ret
; CHECK-LABEL: mscatter_falsemask_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: ret
call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> %val, <4 x i64*> %ptrs, i32 8, <4 x i1> zeroinitializer)
ret void
}
Expand Down Expand Up @@ -1124,13 +1108,9 @@ define void @mscatter_truemask_v4f16(<4 x half> %val, <4 x half*> %ptrs) {
}

define void @mscatter_falsemask_v4f16(<4 x half> %val, <4 x half*> %ptrs) {
; RV32-LABEL: mscatter_falsemask_v4f16:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_falsemask_v4f16:
; RV64: # %bb.0:
; RV64-NEXT: ret
; CHECK-LABEL: mscatter_falsemask_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: ret
call void @llvm.masked.scatter.v4f16.v4p0f16(<4 x half> %val, <4 x half*> %ptrs, i32 2, <4 x i1> zeroinitializer)
ret void
}
Expand Down Expand Up @@ -1320,13 +1300,9 @@ define void @mscatter_truemask_v4f32(<4 x float> %val, <4 x float*> %ptrs) {
}

define void @mscatter_falsemask_v4f32(<4 x float> %val, <4 x float*> %ptrs) {
; RV32-LABEL: mscatter_falsemask_v4f32:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_falsemask_v4f32:
; RV64: # %bb.0:
; RV64-NEXT: ret
; CHECK-LABEL: mscatter_falsemask_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: ret
call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> %val, <4 x float*> %ptrs, i32 4, <4 x i1> zeroinitializer)
ret void
}
Expand Down Expand Up @@ -1579,13 +1555,9 @@ define void @mscatter_truemask_v4f64(<4 x double> %val, <4 x double*> %ptrs) {
}

define void @mscatter_falsemask_v4f64(<4 x double> %val, <4 x double*> %ptrs) {
; RV32-LABEL: mscatter_falsemask_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_falsemask_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: ret
; CHECK-LABEL: mscatter_falsemask_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: ret
call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> %val, <4 x double*> %ptrs, i32 8, <4 x i1> zeroinitializer)
ret void
}
Expand Down
Loading

0 comments on commit f863df9

Please sign in to comment.