[RISCV] Add test cases that show that we're too aggressive about usin…

…g greviw/gorciw. NFC

We currently type legalize to the W form, but type legalization
doesn't place any requirements on the extended bits. So we are ok
to use GREVI/GORCI for type legalization as long as the control
doesn't cross any bits from the extended bits into the lower bits.

This can allow us to recognize cases where the extended bits end
up being all zeros and we can propagate that information through.

My plan is to move greviw/gorciw formation to isel patterns similar
to slliw.

llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZBB
+; RUN: llc -mtriple=riscv64 -mattr=+zbb,+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBP
 
 declare i32 @llvm.riscv.orc.b.i32(i32)
 
@@ -10,6 +12,29 @@ define signext i32 @orcb32(i32 signext %a) nounwind {
 ; RV64ZBB-NEXT:    orc.b a0, a0
 ; RV64ZBB-NEXT:    sext.w a0, a0
 ; RV64ZBB-NEXT:    ret
+;
+; RV64ZBP-LABEL: orcb32:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    gorciw a0, a0, 7
+; RV64ZBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+  ret i32 %tmp
+}
+
+define zeroext i32 @orcb32_zext(i32 zeroext %a) nounwind {
+; RV64ZBB-LABEL: orcb32_zext:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    orc.b a0, a0
+; RV64ZBB-NEXT:    slli a0, a0, 32
+; RV64ZBB-NEXT:    srli a0, a0, 32
+; RV64ZBB-NEXT:    ret
+;
+; RV64ZBP-LABEL: orcb32_zext:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    gorciw a0, a0, 7
+; RV64ZBP-NEXT:    slli a0, a0, 32
+; RV64ZBP-NEXT:    srli a0, a0, 32
+; RV64ZBP-NEXT:    ret
   %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
   ret i32 %tmp
 }
@@ -21,6 +46,11 @@ define i64 @orcb64(i64 %a) nounwind {
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    orc.b a0, a0
 ; RV64ZBB-NEXT:    ret
+;
+; RV64ZBP-LABEL: orcb64:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    orc.b a0, a0
+; RV64ZBP-NEXT:    ret
   %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
   ret i64 %tmp
 }

llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

@@ -34,6 +34,17 @@ define signext i32 @grevi32(i32 signext %a) nounwind {
   ret i32 %tmp
 }
 
+define zeroext i32 @grevi32_zext(i32 zeroext %a) nounwind {
+; RV64ZBP-LABEL: grevi32_zext:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    greviw a0, a0, 13
+; RV64ZBP-NEXT:    slli a0, a0, 32
+; RV64ZBP-NEXT:    srli a0, a0, 32
+; RV64ZBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
+  ret i32 %tmp
+}
+
 declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
 
 define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {