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[mips] Implement add.ps, mul.ps and sub.ps
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Differential revision: https://reviews.llvm.org/D90321
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@michael-roe @atanasyan
michael-roe authored and atanasyan committed Oct 30, 2020
1 parent 36fa658 commit fc0892c
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Showing 20 changed files with 39 additions and 29 deletions.
9 changes: 9 additions & 0 deletions llvm/lib/Target/Mips/MipsInstrFPU.td
View file
Expand Up @@ -452,6 +452,12 @@ let AdditionalPredicates = [NotInMicroMips] in {

let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in {
def FADD_PS64 : ADDS_FT<"add.ps", FGR64Opnd, II_ADD_PS, 0>,
ADDS_FM<0x0, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def FMUL_PS64 : ADDS_FT<"mul.ps", FGR64Opnd, II_MUL_PS, 0>,
ADDS_FM<0x2, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2C, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
Expand All @@ -464,6 +470,9 @@ let DecoderNamespace = "MipsFP64" in {
def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2F, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def FSUB_PS64 : ADDS_FT<"sub.ps", FGR64Opnd, II_SUB_PS, 0>,
ADDS_FM<0x1, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;

def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 22>,
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/Mips/MipsSchedule.td
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Expand Up @@ -26,6 +26,7 @@ def II_ADDIUPC : InstrItinClass;
def II_ADD : InstrItinClass;
def II_ADDU : InstrItinClass;
def II_ADD_D : InstrItinClass;
def II_ADD_PS : InstrItinClass;
def II_ADD_S : InstrItinClass;
def II_ADDR_PS : InstrItinClass;
def II_ALIGN : InstrItinClass;
Expand Down Expand Up @@ -279,6 +280,7 @@ def II_MUL : InstrItinClass;
def II_MUH : InstrItinClass;
def II_MUHU : InstrItinClass;
def II_MULU : InstrItinClass;
def II_MUL_PS : InstrItinClass;
def II_MULR_PS : InstrItinClass;
def II_MULT : InstrItinClass;
def II_MULTU : InstrItinClass;
Expand Down Expand Up @@ -341,6 +343,7 @@ def II_SRLV : InstrItinClass;
def II_SUB : InstrItinClass;
def II_SUBU : InstrItinClass;
def II_SUB_D : InstrItinClass;
def II_SUB_PS : InstrItinClass;
def II_SUB_S : InstrItinClass;
def II_SUXC1 : InstrItinClass;
def II_SW : InstrItinClass;
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/Target/Mips/MipsScheduleGeneric.td
View file
Expand Up @@ -829,10 +829,11 @@ def : InstRW<[GenericWriteFPUL], (instrs ADDR_PS64,
CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L,
CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S,
CVT_PS_S64, CVT_S_PL64, CVT_S_PU64,
CVT_PS_PW64, CVT_PW_PS64,
CVT_PS_PW64, CVT_PW_PS64, FADD_PS64,
FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32,
FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64,
MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, MULR_PS64,
FMUL_PS64, FSUB_PS64, MADD_D32, MADD_D64,
MSUB_D32, MSUB_D64, MULR_PS64,
NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64,
PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64,
ROUND_L_D64, ROUND_L_S, ROUND_W_D32,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/MipsScheduleP5600.td
View file
Expand Up @@ -449,8 +449,8 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>;
// cvt.ps.[sw], cvt.s.(pl|pu), c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps,
// pl[lu].ps, sub.[ds], sub.ps, trunc.w.[ds], trunc.w.ps
def : InstRW<[P5600WriteFPUL],
(instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S,
FSUB_D32, FSUB_D64, FSUB_S)>;
(instrs FADD_D32, FADD_D64, FADD_PS64, FADD_S, FMUL_D32, FMUL_D64,
FMUL_PS64, FMUL_S, FSUB_D32, FSUB_D64, FSUB_PS64, FSUB_S)>;
def : InstRW<[P5600WriteFPUL], (instregex "^TRUNC_(L|W)_(S|D32|D64)$")>;
def : InstRW<[P5600WriteFPUL],
(instregex "^CVT_(S|D32|D64|L|W)_(S|D32|D64|L|W)$")>;
Expand Down
3 changes: 0 additions & 3 deletions llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
View file
Expand Up @@ -7,7 +7,6 @@

.set noat
abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Expand All @@ -32,11 +31,9 @@
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/MC/Mips/mips1/invalid-mips5.s
View file
Expand Up @@ -5,6 +5,7 @@
# RUN: FileCheck %s < %t1

.set noat
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Expand Down Expand Up @@ -71,6 +72,7 @@
movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Expand All @@ -81,6 +83,7 @@
round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Expand Down
3 changes: 0 additions & 3 deletions llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
View file
Expand Up @@ -7,7 +7,6 @@

.set noat
abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Expand All @@ -32,8 +31,6 @@
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3 changes: 3 additions & 0 deletions llvm/test/MC/Mips/mips2/invalid-mips5.s
View file
Expand Up @@ -5,6 +5,7 @@
# RUN: FileCheck %s < %t1

.set noat
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Expand Down Expand Up @@ -67,6 +68,7 @@
movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Expand All @@ -76,6 +78,7 @@
trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
Expand Down
4 changes: 0 additions & 4 deletions llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
View file
Expand Up @@ -7,7 +7,6 @@

.set noat
abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Expand All @@ -32,9 +31,6 @@
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

3 changes: 3 additions & 0 deletions llvm/test/MC/Mips/mips3/invalid-mips5.s
View file
Expand Up @@ -5,6 +5,7 @@
# RUN: FileCheck %s < %t1

.set noat
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Expand All @@ -30,11 +31,13 @@
movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
Expand Down
3 changes: 0 additions & 3 deletions llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
View file
Expand Up @@ -7,7 +7,6 @@

.set noat
abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Expand All @@ -32,8 +31,6 @@
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
3 changes: 3 additions & 0 deletions llvm/test/MC/Mips/mips4/invalid-mips5.s
View file
Expand Up @@ -5,12 +5,15 @@
# RUN: FileCheck %s < %t1

.set noat
add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3 changes: 0 additions & 3 deletions llvm/test/MC/Mips/mips64r2/valid-xfail.s
View file
Expand Up @@ -8,7 +8,6 @@

.set noat
abs.ps $f22,$f8
add.ps $f25,$f27,$f13
addqh.w $s7,$s7,$k1
addqh_r.w $8,$v1,$zero
alnv.ps $f12,$f18,$f30,$12
Expand Down Expand Up @@ -59,7 +58,6 @@
msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16
neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
Expand All @@ -70,7 +68,6 @@
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
sub.ps $f5,$f14,$f26
swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
Expand Down

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