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[AMDGPU] gfx11 EXECZ and VCCZ are no longer allowed to be used as
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sources to SALU and VALU instructions.

Contributors:
Baptiste Saleil <baptiste.saleil@amd.com>

Patch 20/N for upstreaming of AMDGPU gfx11 architecture

Depends on D126989

Reviewed By: rampitec, foad, #amdgpu

Differential Revision: https://reviews.llvm.org/D127143
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@Sisyph
Sisyph committed Jun 10, 2022
1 parent 952e069 commit fd3304e
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Showing 4 changed files with 151 additions and 10 deletions.
20 changes: 20 additions & 0 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View file
Expand Up @@ -1650,6 +1650,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const SMLoc &IDLoc);
bool validateFlatLdsDMA(const MCInst &Inst, const OperandVector &Operands,
const SMLoc &IDLoc);
bool validateExeczVcczOperands(const OperandVector &Operands);
Optional<StringRef> validateLdsDirect(const MCInst &Inst);
unsigned getConstantBusLimit(unsigned Opcode) const;
bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
Expand Down Expand Up @@ -4506,6 +4507,22 @@ bool AMDGPUAsmParser::validateFlatLdsDMA(const MCInst &Inst,
return true;
}

bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
if (!isGFX11Plus())
return true;
for (auto &Operand : Operands) {
if (!Operand->isReg())
continue;
unsigned Reg = Operand->getReg();
if (Reg == SRC_EXECZ || Reg == SRC_VCCZ) {
Error(getRegLoc(Reg, Operands),
"execz and vccz are not supported on this GPU");
return false;
}
}
return true;
}

bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
const SMLoc &IDLoc,
const OperandVector &Operands) {
Expand Down Expand Up @@ -4620,6 +4637,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
return false;
}
if (!validateExeczVcczOperands(Operands)) {
return false;
}

if (!validateFlatLdsDMA(Inst, Operands, IDLoc)) {
return false;
Expand Down
29 changes: 19 additions & 10 deletions llvm/test/MC/AMDGPU/gfx10-constant-bus.s
View file
@@ -1,63 +1,72 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX10 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX11 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX11-ERR --implicit-check-not=error: %s

//-----------------------------------------------------------------------------------------
// On GFX10 we can use two scalar operands (except for 64-bit shift instructions)

v_add_f32 v0, s0, s1
// GFX10: v_add_f32_e64 v0, s0, s1 ; encoding: [0x00,0x00,0x03,0xd5,0x00,0x02,0x00,0x00]
// GCN: v_add_f32_e64 v0, s0, s1 ; encoding: [0x00,0x00,0x03,0xd5,0x00,0x02,0x00,0x00]

v_madak_f32 v0, s0, v1, 42.42
// GFX10: v_madak_f32 v0, s0, v1, 0x4229ae14 ; encoding: [0x00,0x02,0x00,0x42,0x14,0xae,0x29,0x42]
// GFX11-ERR: error: instruction not supported on this GPU

v_med3_f32 v0, s0, s0, s1
// GFX10: v_med3_f32 v0, s0, s0, s1 ; encoding: [0x00,0x00,0x57,0xd5,0x00,0x00,0x04,0x00]
// GFX11: v_med3_f32 v0, s0, s0, s1 ; encoding: [0x00,0x00,0x1f,0xd6,0x00,0x00,0x04,0x00]

//-----------------------------------------------------------------------------------------
// 64-bit shift instructions can use only one scalar value input

v_ashrrev_i64 v[0:1], 0x100, s[0:1]
// GFX10-ERR: error: invalid operand (violates constant bus restrictions)
// GCN-ERR: error: invalid operand (violates constant bus restrictions)

v_ashrrev_i64 v[0:1], s2, s[0:1]
// GFX10-ERR: error: invalid operand (violates constant bus restrictions)
// GCN-ERR: error: invalid operand (violates constant bus restrictions)

//-----------------------------------------------------------------------------------------
// v_div_fmas implicitly reads VCC, so only one scalar operand is possible

v_div_fmas_f32 v5, s3, s3, s3
// GFX10: v_div_fmas_f32 v5, s3, s3, s3 ; encoding: [0x05,0x00,0x6f,0xd5,0x03,0x06,0x0c,0x00]
// GFX11: v_div_fmas_f32 v5, s3, s3, s3 ; encoding: [0x05,0x00,0x37,0xd6,0x03,0x06,0x0c,0x00]

v_div_fmas_f32 v5, s3, s3, s2
// GFX10-ERR: error: invalid operand (violates constant bus restrictions)
// GCN-ERR: error: invalid operand (violates constant bus restrictions)

v_div_fmas_f32 v5, s3, 0x123, v3
// GFX10-ERR: error: invalid operand (violates constant bus restrictions)
// GCN-ERR: error: invalid operand (violates constant bus restrictions)

v_div_fmas_f64 v[5:6], 0x12345678, 0x12345678, 0x12345678
// GFX10: v_div_fmas_f64 v[5:6], 0x12345678, 0x12345678, 0x12345678 ; encoding: [0x05,0x00,0x70,0xd5,0xff,0xfe,0xfd,0x03,0x78,0x56,0x34,0x12]
// GFX11: v_div_fmas_f64 v[5:6], 0x12345678, 0x12345678, 0x12345678 ; encoding: [0x05,0x00,0x38,0xd6,0xff,0xfe,0xfd,0x03,0x78,0x56,0x34,0x12]

v_div_fmas_f64 v[5:6], v[1:2], s[2:3], v[3:4]
// GFX10: v_div_fmas_f64 v[5:6], v[1:2], s[2:3], v[3:4] ; encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0c,0x04]
// GFX11: v_div_fmas_f64 v[5:6], v[1:2], s[2:3], v[3:4] ; encoding: [0x05,0x00,0x38,0xd6,0x01,0x05,0x0c,0x04]

v_div_fmas_f64 v[5:6], v[1:2], s[2:3], 0x123456
// GFX10-ERR: error: invalid operand (violates constant bus restrictions)
// GCN-ERR: error: invalid operand (violates constant bus restrictions)

//-----------------------------------------------------------------------------------------
// v_mad_u64_u32 has operands of different sizes.
// When these operands are literals, they are counted as 2 scalar values even if literals are identical.

v_lshlrev_b64 v[5:6], 0x3f717273, 0x3f717273
// GFX10-ERR: error: invalid operand (violates constant bus restrictions)
// GCN-ERR: error: invalid operand (violates constant bus restrictions)

v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678
// GFX10: v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678 ; encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0xfd,0x03,0x78,0x56,0x34,0x12]
// GFX11: v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678 ; encoding: [0x05,0x0c,0xfe,0xd6,0x01,0xff,0xfd,0x03,0x78,0x56,0x34,0x12]

v_mad_u64_u32 v[5:6], s12, s1, 0x12345678, 0x12345678
// GFX10-ERR: error: invalid operand (violates constant bus restrictions)
// GCN-ERR: error: invalid operand (violates constant bus restrictions)

//-----------------------------------------------------------------------------------------
// null is free

v_bfe_u32 v5, s1, s2, null
// GFX10: v_bfe_u32 v5, s1, s2, null ; encoding: [0x05,0x00,0x48,0xd5,0x01,0x04,0xf4,0x01]
// GFX11: v_bfe_u32 v5, s1, s2, null ; encoding: [0x05,0x00,0x10,0xd6,0x01,0x04,0xf0,0x01]
107 changes: 107 additions & 0 deletions llvm/test/MC/AMDGPU/gfx11_asm_operands.s
View file
@@ -0,0 +1,107 @@
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR %s

// On GFX11+, EXECZ and VCCZ are no longer allowed to be used as sources to SALU and VALU instructions.
// The inline constants are removed. VCCZ and EXECZ still exist and can be use for conditional branches.
// LDS_DIRECT and POPS_EXITING_WAVE_ID are also no longer allowed.

//---------------------------------------------------------------------------//
// EXECZ
//---------------------------------------------------------------------------//

s_cbranch_execz 0x100
// GFX10: encoding: [0x00,0x01,0x88,0xbf]
// GFX11: encoding: [0x00,0x01,0xa5,0xbf]

s_add_i32 s0, execz, s2
// GFX10: encoding: [0xfc,0x02,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

s_add_i32 s0, src_execz, s2
// GFX10: encoding: [0xfc,0x02,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

s_add_i32 s0, s1, execz
// GFX10: encoding: [0x01,0xfc,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

s_add_i32 s0, s1, src_execz
// GFX10: encoding: [0x01,0xfc,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], execz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfc,0x04,0x02,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], src_execz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfc,0x04,0x02,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], v[1:2], execz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf9,0x01,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], v[1:2], src_execz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf9,0x01,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

//---------------------------------------------------------------------------//
// VCCZ
//---------------------------------------------------------------------------//

s_cbranch_vccz 0x100
// GFX10: encoding: [0x00,0x01,0x86,0xbf]
// GFX11: encoding: [0x00,0x01,0xa3,0xbf]

s_add_i32 s0, vccz, s2
// GFX10: encoding: [0xfb,0x02,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

s_add_i32 s0, src_vccz, s2
// GFX10: encoding: [0xfb,0x02,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

s_add_i32 s0, s1, vccz
// GFX10: encoding: [0x01,0xfb,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

s_add_i32 s0, s1, src_vccz
// GFX10: encoding: [0x01,0xfb,0x00,0x81]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], vccz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfb,0x04,0x02,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], src_vccz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfb,0x04,0x02,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], v[1:2], vccz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf7,0x01,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

v_add_f64 v[0:1], v[1:2], src_vccz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf7,0x01,0x00]
// GFX11-ERR: error: execz and vccz are not supported on this GPU

//---------------------------------------------------------------------------//
// LDS_DIRECT
//---------------------------------------------------------------------------//

v_readfirstlane_b32 s0, lds_direct
// GFX10: encoding: [0xfe,0x04,0x00,0x7e]
// GFX11-ERR: error: lds_direct is not supported on this GPU

v_readfirstlane_b32 s0, src_lds_direct
// GFX10: encoding: [0xfe,0x04,0x00,0x7e]
// GFX11-ERR: error: lds_direct is not supported on this GPU

v_mov_b32 v0, lds_direct
// GFX10: encoding: [0xfe,0x02,0x00,0x7e]
// GFX11-ERR: error: lds_direct is not supported on this GPU

v_mov_b32 v0, src_lds_direct
// GFX10: encoding: [0xfe,0x02,0x00,0x7e]
// GFX11-ERR: error: lds_direct is not supported on this GPU
5 changes: 5 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
View file
@@ -1,4 +1,9 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GCN %s
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GFX11 %s

# GCN: warning: invalid instruction encoding
0xdf,0x00,0x00,0x02

# this is buffer_atomic_csub_u32 v5, off, s[8:11], s3 offset:4095. Invalid without glc
# GFX11: warning: invalid instruction encoding
0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x03

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