[X86][FP16] Add tests to show suboptimal codegen, NFC

llvm · Feb 13, 2023 · ff5c00d · ff5c00d
1 parent 9f8ee61
commit ff5c00d
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diff --git a/llvm/test/CodeGen/X86/avx512fp16-cvt.ll b/llvm/test/CodeGen/X86/avx512fp16-cvt.ll
@@ -1027,3 +1027,31 @@ define half @f128_to_half(fp128 %x) nounwind {
   %a = fptrunc fp128 %x to half
   ret half %a
 }
+
+define <8 x half> @s64tof16(<8 x i64> %a) #0 {
+; CHECK-LABEL: s64tof16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvtqq2ps %ymm0, %xmm0
+; CHECK-NEXT:    vcvtqq2ps %ymm1, %xmm1
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vcvtps2phx %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    ret{{[l|q]}}
+  %1 = sitofp <8 x i64> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+define <8 x half> @u64tof16(<8 x i64> %a) #0 {
+; CHECK-LABEL: u64tof16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvtuqq2ps %ymm0, %xmm0
+; CHECK-NEXT:    vcvtuqq2ps %ymm1, %xmm1
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vcvtps2phx %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    ret{{[l|q]}}
+  %1 = uitofp <8 x i64> %a to <8 x half>
+  ret <8 x half> %1
+}
+
+attributes #0 = { "min-legal-vector-width"="256" "prefer-vector-width"="256" }
diff --git a/llvm/test/CodeGen/X86/vec-strict-inttofp-256-fp16.ll b/llvm/test/CodeGen/X86/vec-strict-inttofp-256-fp16.ll
@@ -12,6 +12,8 @@ declare <8 x half> @llvm.experimental.constrained.sitofp.v8f16.v8i32(<8 x i32>,
 declare <8 x half> @llvm.experimental.constrained.uitofp.v8f16.v8i32(<8 x i32>, metadata, metadata)
 declare <4 x half> @llvm.experimental.constrained.sitofp.v4f16.v4i64(<4 x i64>, metadata, metadata)
 declare <4 x half> @llvm.experimental.constrained.uitofp.v4f16.v4i64(<4 x i64>, metadata, metadata)
+declare <8 x half> @llvm.experimental.constrained.sitofp.v8f16.v8i64(<8 x i64>, metadata, metadata)
+declare <8 x half> @llvm.experimental.constrained.uitofp.v8f16.v8i64(<8 x i64>, metadata, metadata)
 
 define <16 x half> @sitofp_v16i1_v16f16(<16 x i1> %x) #0 {
 ; CHECK-LABEL: sitofp_v16i1_v16f16:
@@ -141,4 +143,35 @@ define <4 x half> @uitofp_v4i64_v4f16(<4 x i64> %x) #0 {
   ret <4 x half> %result
 }
 
+define <8 x half> @sitofp_v8i64_v8f16(<8 x i64> %x) #1 {
+; CHECK-LABEL: sitofp_v8i64_v8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvtqq2ps %ymm0, %xmm0
+; CHECK-NEXT:    vcvtqq2ps %ymm1, %xmm1
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vcvtps2phx %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    ret{{[l|q]}}
+ %result = call <8 x half> @llvm.experimental.constrained.sitofp.v8f16.v8i64(<8 x i64> %x,
+                                                              metadata !"round.dynamic",
+                                                              metadata !"fpexcept.strict") #0
+  ret <8 x half> %result
+}
+
+define <8 x half> @uitofp_v8i64_v8f16(<8 x i64> %x) #1 {
+; CHECK-LABEL: uitofp_v8i64_v8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvtuqq2ps %ymm0, %xmm0
+; CHECK-NEXT:    vcvtuqq2ps %ymm1, %xmm1
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vcvtps2phx %ymm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    ret{{[l|q]}}
+ %result = call <8 x half> @llvm.experimental.constrained.uitofp.v8f16.v8i64(<8 x i64> %x,
+                                                              metadata !"round.dynamic",
+                                                              metadata !"fpexcept.strict") #0
+  ret <8 x half> %result
+}
+
 attributes #0 = { strictfp }
+attributes #1 = { strictfp "min-legal-vector-width"="256" "prefer-vector-width"="256" }