[AMDGPU] Add an implicit use of M0 to all V_MOV_B32_indirect_read/write

NFCI. Previously the implicit use was added to V_MOV_B32_indirect_read when building the instruction. V_MOV_B32_indirect_write didn't have an implicit use of M0 at all, but apparently it did not cause any problems. Differential Revision: https://reviews.llvm.org/D114239
llvm · Nov 19, 2021 · ff7f2cf · ff7f2cf
1 parent 2997441
commit ff7f2cf
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Showing 3 changed files with 113 additions and 116 deletions.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1948,8 +1948,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_indirect_read))
         .addDef(Dst)
         .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
-        .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0))
-        .addReg(AMDGPU::M0, RegState::Implicit);
+        .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
 
     MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
 

diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -860,27 +860,25 @@ defm V_CVT_NORM_U16_F16  : VOP1_Real_vi<0x4e>;
 
 defm V_ACCVGPR_MOV_B32   : VOP1Only_Real_vi<0x52>;
 
+let VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [EXEC, M0] in {
+
 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
 // indexing mode. vdst can't be treated as a def for codegen purposes,
 // and an implicit use and def of the super register should be added.
 def V_MOV_B32_indirect_write : VPseudoInstSI<(outs),
   (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>,
   PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
-                                        getVOPSrc0ForVT<i32>.ret:$src0)> {
-  let VOP1 = 1;
-  let SubtargetPredicate = isGFX8GFX9;
-}
+                                        getVOPSrc0ForVT<i32>.ret:$src0)>;
 
 // Copy of v_mov_b32 for use with VGPR indexing mode. An implicit use of the
 // super register should be added.
 def V_MOV_B32_indirect_read : VPseudoInstSI<
   (outs getVALUDstForVT<i32>.ret:$vdst),
   (ins getVOPSrc0ForVT<i32>.ret:$src0)>,
   PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
-                                        getVOPSrc0ForVT<i32>.ret:$src0)> {
-  let VOP1 = 1;
-  let SubtargetPredicate = isGFX8GFX9;
-}
+                                        getVOPSrc0ForVT<i32>.ret:$src0)>;
+
+} // End VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [M0]
 
 let OtherPredicates = [isGFX8Plus] in {