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[X86][MC] Teach disassembler to recognize apx instructions which igno…
…res W bit (#82747) Extended VMX instructions and 8 bit apx extended instructions don't need W bit, they are marked as W ignored in spec. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT | ||
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL | ||
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## invpcid | ||
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# ATT: invpcid 123(%rax,%rbx,4), %r9 | ||
# INTEL: invpcid r9, xmmword ptr [rax + 4*rbx + 123] | ||
0x62,0x74,0xfe,0x08,0xf2,0x4c,0x98,0x7b | ||
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# ATT: invpcid 291(%r28,%r29,4), %r19 | ||
# INTEL: invpcid r19, xmmword ptr [r28 + 4*r29 + 291] | ||
0x62,0x8c,0xfa,0x08,0xf2,0x9c,0xac,0x23,0x01,0x00,0x00 | ||
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## invept | ||
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# ATT: invept 291(%r28,%r29,4), %r19 | ||
# INTEL: invept r19, xmmword ptr [r28 + 4*r29 + 291] | ||
0x62,0x8c,0xfa,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00 | ||
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# ATT: invept 123(%rax,%rbx,4), %r9 | ||
# INTEL: invept r9, xmmword ptr [rax + 4*rbx + 123] | ||
0x62,0x74,0xfe,0x08,0xf0,0x4c,0x98,0x7b | ||
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## invvpid | ||
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# ATT: invvpid 291(%r28,%r29,4), %r19 | ||
# INTEL: invvpid r19, xmmword ptr [r28 + 4*r29 + 291] | ||
0x62,0x8c,0xfa,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00 | ||
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# ATT: invvpid 123(%rax,%rbx,4), %r9 | ||
# INTEL: invvpid r9, xmmword ptr [rax + 4*rbx + 123] | ||
0x62,0x74,0xfe,0x08,0xf1,0x4c,0x98,0x7b | ||
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## adc | ||
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# ATT: {evex} adcb $123, %bl | ||
# INTEL: {evex} adc bl, 123 | ||
0x62,0xf4,0xfc,0x08,0x80,0xd3,0x7b | ||
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# ATT: adcb $123, %bl, %cl | ||
# INTEL: adc cl, bl, 123 | ||
0x62,0xf4,0xf4,0x18,0x80,0xd3,0x7b | ||
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# ATT: adcb $123, %r16b | ||
# INTEL: adc r16b, 123 | ||
0xd5,0x18,0x80,0xd0,0x7b | ||
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## add | ||
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# ATT: {evex} addb $123, %bl | ||
# INTEL: {evex} add bl, 123 | ||
0x62,0xf4,0xfc,0x08,0x80,0xc3,0x7b | ||
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# ATT: {nf} addb $123, %bl | ||
# INTEL: {nf} add bl, 123 | ||
0x62,0xf4,0xfc,0x0c,0x80,0xc3,0x7b | ||
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# ATT: addb $123, %bl, %cl | ||
# INTEL: add cl, bl, 123 | ||
0x62,0xf4,0xf4,0x18,0x80,0xc3,0x7b | ||
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# ATT: {nf} addb $123, %bl, %cl | ||
# INTEL: {nf} add cl, bl, 123 | ||
0x62,0xf4,0xf4,0x1c,0x80,0xc3,0x7b | ||
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# ATT: addb $123, %r16b | ||
# INTEL: add r16b, 123 | ||
0xd5,0x18,0x80,0xc0,0x7b | ||
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## inc | ||
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# ATT: {evex} incb %bl | ||
# INTEL: {evex} inc bl | ||
0x62,0xf4,0xfc,0x08,0xfe,0xc3 | ||
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# ATT: {nf} incb %bl | ||
# INTEL: {nf} inc bl | ||
0x62,0xf4,0xfc,0x0c,0xfe,0xc3 | ||
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# ATT: incb %bl, %bl | ||
# INTEL: inc bl, bl | ||
0x62,0xf4,0xe4,0x18,0xfe,0xc3 | ||
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# ATT: {nf} incb %bl, %bl | ||
# INTEL: {nf} inc bl, bl | ||
0x62,0xf4,0xe4,0x1c,0xfe,0xc3 | ||
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# ATT: incb %r16b | ||
# INTEL: inc r16b | ||
0xd5,0x18,0xfe,0xc0 | ||
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## mul | ||
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# ATT: {evex} mulb %bl | ||
# INTEL: {evex} mul bl | ||
0x62,0xf4,0xfc,0x08,0xf6,0xe3 | ||
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# ATT: {nf} mulb %bl | ||
# INTEL: {nf} mul bl | ||
0x62,0xf4,0xfc,0x0c,0xf6,0xe3 | ||
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# ATT: mulb %r16b | ||
# INTEL: mul r16b | ||
0xd5,0x18,0xf6,0xe0 | ||
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## imul | ||
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# ATT: {evex} imulb %bl | ||
# INTEL: {evex} imul bl | ||
0x62,0xf4,0xfc,0x08,0xf6,0xeb | ||
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# ATT: {nf} imulb %bl | ||
# INTEL: {nf} imul bl | ||
0x62,0xf4,0xfc,0x0c,0xf6,0xeb | ||
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# ATT: imulb %r16b | ||
# INTEL: imul r16b | ||
0xd5,0x18,0xf6,0xe8 |
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