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[VE] VEC_BROADCAST, lowering and isel
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This defines the vec_broadcast SDNode along with lowering and isel code.
We also remove unused type mappings for the vector register classes (all vector MVTs that are not used in the ISA go).

We will implement support for short vectors later by intercepting nodes with illegal vector EVTs before LLVM has had a chance to widen them.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D91646
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@simoll
simoll committed Nov 19, 2020
1 parent 1827005 commit ffe6c97
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Showing 7 changed files with 426 additions and 65 deletions.
18 changes: 2 additions & 16 deletions llvm/lib/Target/VE/VECallingConv.td
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Original file line number Diff line number Diff line change
Expand Up @@ -103,14 +103,7 @@ def RetCC_VE_C : CallingConv<[
// handled conforming to the standard cc.
def CC_VE_Fast : CallingConv<[
// vector --> generic vector registers
CCIfType<[v2i32, v2i64, v2f32, v2f64,
v4i32, v4i64, v4f32, v4f64,
v8i32, v8i64, v8f32, v8f64,
v16i32, v16i64, v16f32, v16f64,
v32i32, v32i64, v32f32, v32f64,
v64i32, v64i64, v64f32, v64f64,
v128i32, v128i64, v128f32, v128f64,
v256i32, v256f32, v256i64, v256f64],
CCIfType<[v256i32, v256f32, v256i64, v256f64],
CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
// TODO: make this conditional on packed mode
CCIfType<[v512i32, v512f32],
Expand All @@ -131,14 +124,7 @@ def CC_VE_Fast : CallingConv<[

def RetCC_VE_Fast : CallingConv<[
// vector --> generic vector registers
CCIfType<[v2i32, v2i64, v2f32, v2f64,
v4i32, v4i64, v4f32, v4f64,
v8i32, v8i64, v8f32, v8f64,
v16i32, v16i64, v16f32, v16f64,
v32i32, v32i64, v32f32, v32f64,
v64i32, v64i64, v64f32, v64f64,
v128i32, v128i64, v128f32, v128f64,
v256i32, v256f32, v256i64, v256f64],
CCIfType<[v256i32, v256f32, v256i64, v256f64],
CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
// TODO: make this conditional on packed mode
CCIfType<[v512i32, v512f32],
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81 changes: 40 additions & 41 deletions llvm/lib/Target/VE/VEISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,11 @@ bool VETargetLowering::CanLowerReturn(
return CCInfo.CheckReturn(Outs, RetCC);
}

static const MVT AllVectorVTs[] = {MVT::v256i32, MVT::v512i32, MVT::v256i64,
MVT::v256f32, MVT::v512f32, MVT::v256f64};

static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1};

void VETargetLowering::initRegisterClasses() {
// Set up the register classes.
addRegisterClass(MVT::i32, &VE::I32RegClass);
Expand All @@ -79,46 +84,10 @@ void VETargetLowering::initRegisterClasses() {
addRegisterClass(MVT::f128, &VE::F128RegClass);

if (Subtarget->enableVPU()) {
addRegisterClass(MVT::v2i32, &VE::V64RegClass);
addRegisterClass(MVT::v4i32, &VE::V64RegClass);
addRegisterClass(MVT::v8i32, &VE::V64RegClass);
addRegisterClass(MVT::v16i32, &VE::V64RegClass);
addRegisterClass(MVT::v32i32, &VE::V64RegClass);
addRegisterClass(MVT::v64i32, &VE::V64RegClass);
addRegisterClass(MVT::v128i32, &VE::V64RegClass);
addRegisterClass(MVT::v256i32, &VE::V64RegClass);
addRegisterClass(MVT::v512i32, &VE::V64RegClass);

addRegisterClass(MVT::v2i64, &VE::V64RegClass);
addRegisterClass(MVT::v4i64, &VE::V64RegClass);
addRegisterClass(MVT::v8i64, &VE::V64RegClass);
addRegisterClass(MVT::v16i64, &VE::V64RegClass);
addRegisterClass(MVT::v32i64, &VE::V64RegClass);
addRegisterClass(MVT::v64i64, &VE::V64RegClass);
addRegisterClass(MVT::v128i64, &VE::V64RegClass);
addRegisterClass(MVT::v256i64, &VE::V64RegClass);

addRegisterClass(MVT::v2f32, &VE::V64RegClass);
addRegisterClass(MVT::v4f32, &VE::V64RegClass);
addRegisterClass(MVT::v8f32, &VE::V64RegClass);
addRegisterClass(MVT::v16f32, &VE::V64RegClass);
addRegisterClass(MVT::v32f32, &VE::V64RegClass);
addRegisterClass(MVT::v64f32, &VE::V64RegClass);
addRegisterClass(MVT::v128f32, &VE::V64RegClass);
addRegisterClass(MVT::v256f32, &VE::V64RegClass);
addRegisterClass(MVT::v512f32, &VE::V64RegClass);

addRegisterClass(MVT::v2f64, &VE::V64RegClass);
addRegisterClass(MVT::v4f64, &VE::V64RegClass);
addRegisterClass(MVT::v8f64, &VE::V64RegClass);
addRegisterClass(MVT::v16f64, &VE::V64RegClass);
addRegisterClass(MVT::v32f64, &VE::V64RegClass);
addRegisterClass(MVT::v64f64, &VE::V64RegClass);
addRegisterClass(MVT::v128f64, &VE::V64RegClass);
addRegisterClass(MVT::v256f64, &VE::V64RegClass);

addRegisterClass(MVT::v256i1, &VE::VMRegClass);
addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
for (MVT VecVT : AllVectorVTs)
addRegisterClass(VecVT, &VE::V64RegClass);
for (MVT MaskVT : AllMaskVTs)
addRegisterClass(MaskVT, &VE::VMRegClass);
}
}

Expand Down Expand Up @@ -285,7 +254,8 @@ void VETargetLowering::initSPUActions() {
}

void VETargetLowering::initVPUActions() {
// TODO upstream vector isel
for (MVT LegalVecVT : AllVectorVTs)
setOperationAction(ISD::BUILD_VECTOR, LegalVecVT, Custom);
}

SDValue
Expand Down Expand Up @@ -898,6 +868,7 @@ const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const {
TARGET_NODE_CASE(GETTLSADDR)
TARGET_NODE_CASE(MEMBARRIER)
TARGET_NODE_CASE(CALL)
TARGET_NODE_CASE(VEC_BROADCAST)
TARGET_NODE_CASE(RET_FLAG)
TARGET_NODE_CASE(GLOBAL_BASE_REG)
}
Expand Down Expand Up @@ -1403,6 +1374,32 @@ SDValue VETargetLowering::lowerDYNAMIC_STACKALLOC(SDValue Op,
return DAG.getMergeValues(Ops, DL);
}

static SDValue getSplatValue(SDNode *N) {
if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(N)) {
return BuildVec->getSplatValue();
}
return SDValue();
}

SDValue VETargetLowering::lowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
unsigned NumEls = Op.getValueType().getVectorNumElements();
MVT ElemVT = Op.getSimpleValueType().getVectorElementType();

if (SDValue ScalarV = getSplatValue(Op.getNode())) {
// lower to VEC_BROADCAST
MVT LegalResVT = MVT::getVectorVT(ElemVT, 256);

auto AVL = DAG.getConstant(NumEls, DL, MVT::i32);
return DAG.getNode(VEISD::VEC_BROADCAST, DL, LegalResVT, Op.getOperand(0),
AVL);
}

// Expand
return SDValue();
}

SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default:
Expand All @@ -1423,6 +1420,8 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
return lowerJumpTable(Op, DAG);
case ISD::LOAD:
return lowerLOAD(Op, DAG);
case ISD::BUILD_VECTOR:
return lowerBUILD_VECTOR(Op, DAG);
case ISD::STORE:
return lowerSTORE(Op, DAG);
case ISD::VASTART:
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/VE/VEISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,8 @@ enum NodeType : unsigned {

MEMBARRIER, // Compiler barrier only; generate a no-op.

VEC_BROADCAST, // 0: scalar value, 1: VL

CALL, // A call instruction.
RET_FLAG, // Return with a flag operand.
GLOBAL_BASE_REG, // Global base reg for PIC.
Expand Down Expand Up @@ -114,6 +116,8 @@ class VETargetLowering : public TargetLowering {
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;

SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
/// } Custom Lower

/// Custom DAGCombine {
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/VE/VEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2224,3 +2224,6 @@ include "VEInstrVec.td"

// The vevlintrin
include "VEInstrIntrinsicVL.td"

// Patterns and intermediate SD nodes (VEC_*).
include "VEInstrPatternsVec.td"
48 changes: 48 additions & 0 deletions llvm/lib/Target/VE/VEInstrPatternsVec.td
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Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
//===-- VEInstrPatternsVec.td - VEC_-type SDNodes and isel for VE Target --===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the VEC_* prefixed intermediate SDNodes and their
// isel patterns.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//

// Custom intermediate ISDs.
class IsVLVT<int OpIdx> : SDTCisVT<OpIdx,i32>;
def vec_broadcast : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2, [SDTCisVec<0>, IsVLVT<2>]>>;

multiclass vbrd_elem32<ValueType v32, ValueType s32, SDPatternOperator ImmOp, SDNodeXForm ImmCast, int SubRegIdx> {
// VBRDil
def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)),
(VBRDil (ImmCast $sy), i32:$vl)>;

// VBRDrl
def : Pat<(v32 (vec_broadcast s32:$sy, i32:$vl)),
(VBRDrl
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, SubRegIdx),
i32:$vl)>;
}

defm : vbrd_elem32<v256f32, f32, simm7fp, LO7FP, sub_f32>;
defm : vbrd_elem32<v256i32, i32, simm7, LO7, sub_i32>;

multiclass vbrd_elem64<ValueType v64, ValueType s64, SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
// VBRDil
def : Pat<(v64 (vec_broadcast (s64 ImmOp:$sy), i32:$vl)),
(VBRDil (ImmCast $sy), i32:$vl)>;

// VBRDrl
def : Pat<(v64 (vec_broadcast s64:$sy, i32:$vl)),
(VBRDrl s64:$sy, i32:$vl)>;
}

defm : vbrd_elem64<v256f64, f64, simm7fp, LO7FP>;
defm : vbrd_elem64<v256i64, i64, simm7, LO7>;
9 changes: 1 addition & 8 deletions llvm/lib/Target/VE/VERegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -185,14 +185,7 @@ def F128 : RegisterClass<"VE", [f128], 128,
def V64 : RegisterClass<"VE",
[v256f64, // default type for vector registers
v512i32, v512f32,
v256i64, v256i32, v256f32, /* v256f64, */
v128i64, v128i32, v128f32, v128f64,
v64i64, v64i32, v64f32, v64f64,
v32i64, v32i32, v32f32, v32f64,
v16i64, v16i32, v16f32, v16f64,
v8i64, v8i32, v8f32, v8f64,
v4i64, v4i32, v4f32, v4f64,
v2i64, v2i32, v2f32, v2f64], 64,
v256i64, v256i32, v256f32, /* v256f64, */], 64,
(add (sequence "V%u", 0, 63),
VIX)>;

Expand Down
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