SimplifyDemandedBitsForTargetNode - Missing AArch64ISD::BIC & AArch64ISD::BICi handling

[RKSimon]

These get lowered quite early, meaning that there are missed opportunities to further simplify the DAG based on the masked bits.

Noticed while looking at Issue #53622

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

[llvmbot]

@llvm/issue-subscribers-good-first-issue

[sjoerdmeijer]

Hi @RKSimon, can you expand a little bit what the idea of this work is? Do we expect that it triggers a rewrite?

[RKSimon]

@sjoerdmeijer I'll try to find the work I was doing on #53622 and see if I can repro

[RKSimon]

@davemgreen @sjoerdmeijer This is the kind of thing I had in mind: https://rust.godbolt.org/z/M6WbxTaYv

define <8 x i16> @haddu_known(<8 x i8> %a0, <8 x i8> %a1) {
  %x0 = zext <8 x i8> %a0 to <8 x i16>
  %x1 = zext <8 x i8> %a1 to <8 x i16>
  %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
  %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
  ret <8 x i16> %res
}
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)

->

Combining: t0: ch,glue = EntryToken
Optimized lowered selection DAG: %bb.0 'haddu_known:'
SelectionDAG has 15 nodes:
  t0: ch,glue = EntryToken
          t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
        t5: v8i16 = zero_extend t2
          t4: v8i8,ch = CopyFromReg t0, Register:v8i8 %1
        t6: v8i16 = zero_extend t4
      t8: v8i16 = llvm.aarch64.neon.uhadd TargetConstant:i64<635>, t5, t6
    t18: v8i16 = AArch64ISD::BICi t8, Constant:i32<254>, Constant:i32<8>
  t13: ch,glue = CopyToReg t0, Register:v8i16 $q0, t18
  t14: ch = AArch64ISD::RET_GLUE t13, Register:v8i16 $q0, t13:1

The AND should be removable as the uhadd (ISD::AVGFLOORU) node should never have the top most bits set, but the AND gets coverted to a AArch64ISD::BICi node very early, so we need:

• SelectionDAG::computeKnownBits to handle ISD::AVGFLOORU nodes (this is a very basic extension of the ISD::AVGCEILU handling from D119629 for [DAG] Add knownbits/signbits handling for ISD::AVG* nodes #53622)
• SimplifyDemandedBitsForTargetNode handling for AArch64ISD::BICi to correctly grab the known bits for the input operand and realise the AArch64ISD::BICi is superfluous.

[snikitav]

May I take this one?

[RKSimon]

Sure, go for it

[RKSimon]

#53622 needs addressing as well if you're interested :)

[snikitav]

Sure

[snikitav]

@RKSimon could you please assign it to me so no one will be confused? and #53622 as well

[snikitav]

@RKSimon could you please provide an example similar to https://rust.godbolt.org/z/M6WbxTaYv but with BIC instead of BICi. Because I don't see how this optimization could be applied to BIC version without immediate, sorry.

#76644 PTAL

[RKSimon]

It wasn't necessarily for HADD etc. But you should be able to at least use KnownBits getMinValue/getMaxValue bounds to work out the known upper zero bits etc.